IBM PC 300GL manual PCI Bus, IDE bus master interface, USB interface

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PCI Bus

The PCI bus originates in the chip set. Features of the PCI bus are:

•Integrated arbiter with multitransaction PCI arbitration acceleration hooks

•Zero-wait-state, microprocessor-to-PCI write interface for high-performance graphics

•Built-in PCI bus arbiter

•Microprocessor-to-PCI memory write posting

•Conversion of back-to-back, sequential, microprocessor-to-PCI memory write to PCI burst write

•Delayed transaction

•PCI parity checking and generation support

IDE bus master interface

The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with Extensions.

The bus master for the IDE interface is integrated into the I/O hub of the

chip set. The chip set is PCI 2.2 compliant. It connects directly to the PCI bus and is designed to allow concurrent operations on the PCI bus and IDE bus. The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA mode 0–3 devices. Ultra DMA 66 transfers up to 66 Mbps using an ATA 66 cable.

The IDE devices receive their power through a four-position power cable containing +5 V dc, +12 V dc, and ground voltage. As devices are added to the IDE interface, designate one device as the master, or primary, device and another as the slave, or subordinate, device. These designations are determined by switches or jumpers on each device. There are two IDE ports, one designated Primary and the other Secondary, allowing for up to four devices to be attached. The total number of physical IDE devices is determined by available space on the system board.

For the IDE interface, no resource assignments are given in the system memory or the direct memory access (DMA) channels. For information on the resource assignments, see “Input/output address map” on page 48 and “Appendix C. IRQ and DMA channel assignments,” on page 53.

For information on the connector pin assignments, see “IDE connectors” on page 42.

USB interface

Universal Serial Bus (USB) technology is a standard feature of your personal computer. The system board provides the USB interface with two connectors integrated into the chip set. A USB-enabled device can attach to a connector and, if that device is a hub, multiple peripheral devices can attach to the hub and be used by the system. The USB connectors use Plug and Play technology for installed devices. The speed of the USB is up to 12 MBps with a maximum of 127 peripheral devices. The USB is compliant with Universal Host Controller Interface Guide 1.0.

Features of USB technology include:

•Plug and Play devices

•Concurrent operation of multiple devices

•Suitability for different device bandwidths

Chapter 2. System board features 7

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Contents HcchM mlmiM mlni hcc mlml HcchM mlmiM mlni hcc mlml Second Edition March Contents Page Preface Related publicationsTerminology Features System OverviewCD-RW Wake on Ring Adsl modemsWake on LAN PC 300 GL and 300 PL L2 Cache System board featuresIntel Pentium III microprocessor with MMX technology Chip set controlTable . Memory Configuration MB Total Memory Mem O USB interface PCI BusIDE bus master interface Video Subsystem RAM Video subsystem resources Resource AssignmentROM IRQAudio Subsystem Serial ports Integrated peripheral controllerDiskette Drive Interface Parallel port Keyboard and mouse portsFlash Eeprom Network connectionReal-time clock and Cmos Expansion adaptersPhysical layout Rocker switches ÝdimmLarge rocker switch settings Microprocessor Speed Small rocker switch settings Function Cable connectorsConnector panel 18 PC 300 GL and 300 PL USB 20 PC 300 GL and 300 PL Physical specifications PC 300 GL and PL desktopAirflow PC300 PL and GL towerHeat output Acoustical noise-emission valuesPhysical specifications 24 PC 300 GL and 300 PL Power output Power supplyPower input Power input requirements Specification MeasurementsKeyboard port Supply voltage Maximum current Tolerance Component outputsSystem board Supply voltage Maximum current Tolerance USB port Supply voltage Maximum current ToleranceVideo port pin Supply voltage Maximum current Tolerance Connector descriptionOutput protection 28 PC 300 GL and 300 PL System software Plug and PlayAdvanced Configuration and Power Interface Acpi Configuration/Setup Utility programAdvanced Power Management APM Flash update utility programHardware interrupts System compatibilityHardware compatibility Machine-sensitive programs Software compatibilitySoftware interrupts Svga monitor port connector pin assignments Pin Signal Appendix A. Connector pin assignmentsSvga monitor connector DDC2BDVI-I monitor connector System memory connectorDQ2 VSS DQ0DQ1 DQ3CKE0 BA0 BA1CK1 CK0 DQMB2System memory connector pin input/output Pin Signal name CAS# DQMB0# GNDVDD WE# DQMB4# DQMB1#SA0 SDA VrefGND CK2 SA0 VDDPCI connectors PCI connector pin assignments Pin SignalTRDY# FRAME#IRDY# DEVSEL#IDE connectors IDE connector pin assignments Pin SignalMSEN0 Diskette drive connectorDiskette drive connector pin assignments Pin Signal MSEN1USB port connectors Power supply connectorWake on LAN connectors Mouse port connector pin assignments Pin Signal Mouse and keyboard port connectorsSerial port connector Keyboard port connector pin assignments Pin SignalParallel port connector Parallel port connector pin assignments Pin SignalFFFE0000-FFFFFFFF Appendix B. System address mapsSystem memory map LPT3 Input/output address mapO address map Address hex Size Description LPT1 COM2LPT2 COM1DMA I/O address map PCI configuration space map 52 PC 300 GL and 300 PL System resource Appendix C. IRQ and DMA channel assignmentsIRQ channel assignments DMA channel assignments Data width System resource Beep codes Appendix D. Error codesPost error codes 56 PC 300 GL and 300 PL Appendix E. Notices and Trademarks IBM58 PC 300 GL and 300 PL Bibliography 60 PC 300 GL and 300 PL Index PCIUart
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