IBM PC 300PL manual PCI bus, IDE bus master interface, USB interface

Chapter 2. System board features

PCI bus

The fully synchronous 33 MHz PCI bus originates in the chip set. Features of the PCI

Ÿ	Integrated arbiter	with multitransaction PCI arbitration acceleration			hooks
Ÿ	Zero-wait-state, microprocessor-to-PCI write interface for high-performance					graphics
Ÿ	Built-in PCI bus arbiter with support for up to five masters
Ÿ	Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
Ÿ	Conversion of back-to-back		sequential microprocessor-to-PCI memory	write	to	PCI	burst	wri
Ÿ	PCI-to-DRAM posting 18	Dwords
Ÿ	PCI-to-DRAM up to 100+ MB/sec bandwidth
Ÿ	Multitransaction timer	to	support multiple short PCI transactions	within	one	PCI	ARB	cycl
Ÿ	PCI 2.2 compliant

ŸDelayed transaction

ŸPCI parity checking and generation support

IDE bus master interface

The system board incorporates a PCI-to-IDE interface thatAT Attachmentcomplies Inwitherfacethe with Extensions.

The

bus

master

for the

IDE

interface

is integrated into the I/O hub of the Intel

is PCI

2.2

compliant. It

connects

directly

to

the PCI

bus

and

is

designed

to

allow c

the

PCI

bus and IDE bus. The chip

set

is capable

of

supporting

PIO

mode

0–4

device

mode

0–3 devices,

ATA

66

transfers up to 66 megabytes per second (MBps).

The

IDE

devices

receive

their

power

through a four-position power cable containing +5,

voltage. When devices are added to the

IDE

interface,

one device

is

designated

as

another

is designated

as

the

slave

or

subordinate

device. These

designations

are

det

or jumpers on each device. There are

two IDE ports, one designated Primary and the

allowing

for

up

to

four

devices

to

be

attached. The

total

number

of physical

IDE

de

the

mechanical

package.

For

the

IDE

interface,

no resource assignments are given in the system memory or the

access

(DMA)

channels. For

information

on

the

resource

assignments,

see

“Input/output addre

page 36

and

Figure 38

on

page 40

(for

IRQ

assignments).

Two connectors are provided on the riser card for the IDE interface. For information assignments, see “IDE connectors” on page 30.

USB interface

Universal Serial Bus (USB)

technology

is

a

standard

feature of

the computer.

The

syst

the USB interface with two

connectors

integrated into

the

ICH1

(I/O

hub)

in

the chi

device

can

attach

to

a

connector,

and

if

that

device

is

a

hub,

multiple

peripheral

hub and

be

used

by

the

system. The

USB

connectors

use

Plug

and

Play

technology

for

The speed of the USB

is

up to 12 MB/sec with a maximum

of

127

peripheral

devices.

compliant

with Universal

Host

Controller Interface

Guide

1.0.

6 Technical Information Manual