IBM PC 300PL manual System compatibility, Hardware compatibility, Hardware interrupts, Eoi

Page 31

Chapter 6. System compatibility

Chapter 6. System compatibility

This

chapter discusses some

of

the

hardware,

software,

and

BIOS compatibility issue

See

theCompatibility Reportfor a

list

of

compatible

hardware

and

software options.

Hardware compatibility

This section discusses hardware, software, and BIOS compatibility issues that must b designing application programs.

Many

of the

interfaces

are the

same

as those used by

the IBM Personal Computer AT

the

command

and status

organization

of

these interfaces is

maintained.

The functional interfaces are compatible with the following interfaces:

Ÿ

Intel

8259 interrupt controllers (edge-triggered mode)

 

Ÿ

National

Semiconductor

NS16450 and NS16550A serial communication controllers

Ÿ

Motorola

MC146818 Time

of

Day

Clock

command

and status (CMOS

reorganized)

Ÿ

Intel

8254 timer, driven

from

a

1.193

MHz clock (channels

0, 1, and 2)

ŸIntel 8237 DMA controller, except for the Command and Request registers and the R

functions; the Mode register is partially supported

Ÿ

Intel

8272 or 82077 diskette

drive

controllers

 

 

 

 

Ÿ

Intel

8042 keyboard

controller

at

addresses

hex

0060 and

hex

0064

Ÿ

All video standards using VGA,

EGA,

CGA, MDA, and Hercules modes

 

Ÿ

Parallel

printer ports

(Parallel

1,

Parallel 2,

and

Parallel

3) in

compatibility mode

Use this information to develop application programs. Whenever possible, use the BIOS hardware to provide maximum compatibility and portability of applications among systems.

Hardware interrupts

Hardware interrupts are level-sensitive for PCI interrupts. The interrupt controller clea register bit when the interrupt routine sends an End-of-Interrupt (EOI) command to the command is sent regardless of whether the incoming interrupt request to the controller inactive.

The interrupt-in-progress latch is readable at an I/O-address bit position. This latch interrupt service routine and might be reset by the read operation or it might re

Note: For performance and latency considerations, designers might want to limit the numbe sharing an interrupt level.

With level-sensitive interrupts, the

interrupt

controller requires that the

interrupt

re

time the

EOI

command is sent; otherwise, a

new interrupt request will be detected.

level-sensitive

interrupt handler must

clear

the interrupt

condition (usually

by a read

an I/O

port

on the device causing

the

interrupt). After

processing the

interrupt,

th

1.Clears the interrupt

2.Waits one I/O delay

3.Sends the EOI

Copyright IBM Corp. September 1999

23

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Contents Page With 1999Apply AreContents Post BiosError codes System softwareReferences Index Contents USB port Internal Dasd Recovery jumper Power-input requirementsVii PrefaceRelated publications Terminology usageBytes, and2 073 824 EqualsExpressing storage Capacity Equals System overview Major featuresSystem overview PCI Other featuresPOST/BIOS Network supportOn Ring System FeaturesSystem board features FeaturesRimm System memoryIDE bus master interface PCI busUSB interface Bus Video subsystemResource Assignment Interface Plug Play support Advanced PowerList Bus Mastering Support For Fast Performance 64-bit 125 Video subsystem resourcesMonitor support FeaturesAudio subsystem Port Super input/output controllerDiskette Drive interface Seria l portsNetwork connection Keyboard and mouse portsRPL Physical layout System board features Real-timeFlash Eeprom Expansion adaptersRiser card layouts System board, Types 6584DVI Recovery jumperCable connectors Recovery jumperSystem board Connector panelNIC Physical specificationsThis Section Lists Physical Specifications For Types 6584 and 6594.AUX5 TowerRequirements For Wake LAN adapters Have Pin Right-angle Header ForPower supply Power supplyPower input Power outputComponents draw less current than Maximum Shown Component outputsOutput protection Connector descriptionPlay System softwareSystem software Utility Flash update utility programDiagnostic program Configuration/SetupSystem compatibility System compatibilityHardware compatibility Hardware interruptsMachine-sensitive programs Hard disk drives and controllerSoftware compatibility Software interruptsMonitor port connector pin assignments-SVGA Appendix A. Connector pin assignmentsMonitor connector Appendix A. Connector pin assignmentsPin assignments Memory connectorsSystem memory connector pin assignments Pin SignalPin Assignments PCI connector pin assignmentsPin ConnectorFor pin A41 Connector slot One Only For All Other slots, the signalConnectors Are on Riser card These Assignments Are ForIDE connector pin assignments IDE connectorsPin Signal name ConnectorDiskette drive connector pin assignments Power supply connector pin assignmentsRadio frequency identification Rfid pin assignments Alert on LAN connectorsTamper detection switch Connector pinKeyboard CD audio connectorUSB port connectors PortConnector Keyboard port connector pin assignmentsSerial port connector pin assignments Parallel port connector pin assignmentsPin Signal Ground Appendix Appendix B. System address mapsSystem Input/outputO address map MapsBits Byte Pointer Are ReservedDMA I/O address map Hex Size DescriptionMap ConfigurationSystem address maps DMA channel assignments Appendix C. IRQ and DMA channel assignmentsAppendix C. IRQ and DMA channel assignments IRQ channel assignmentsBeep codes Appendix D. Error codesAppendix D. Error Codes CodesReferences This Publication Appendix E. Notices and trademarksReference Specification Advanced PowerReferences Index ConnectorIndex Memory Features Wake on LAN 2 Wake on RingRfid
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