IBM PC 300PL manual Are Reserved, DMA I/O address map, Hex Size Description, Bits Byte Pointer

Appendix B. System address maps

Figure		36	(Page 3 of		3). I/O address map
Address	(Hex)			Size			Description
0490–0CF7				1912		bytes	Available
0CF8–0CFB				4	bytes		PCI	Configuration	address register
0CFC–0CFF				4	bytes		PCI	Configuration	data register
LPT n	+	400h		8	bytes		ECP	port, LPTn base address+ hex 400
0CF9				1	byte		Turbo and reset control register
0D00–FFFF				62207		bytes	Available

DMA

I/O

address

map

The

following figure

lists

resource

assignments

for

the DMA

address map. Any addresses

shown

are

reserved.

Figure

37

(Page

1

of

2).

DMA I/O address map

Address (hex)

Description

Bits

Byte

pointer

0000

Channel 0, Memory Address register

00–15

Yes

0001

Channel 0, Transfer Count register

00–15

Yes

0002

Channel 1, Memory Address register

00–15

Yes

0003

Channel 1, Transfer Count register

00–15

Yes

0004

Channel 2, Memory Address register

00–15

Yes

0005

Channel 2, Transfer Count register

00–15

Yes

0006

Channel 3, Memory Address register

00–15

Yes

0007

Channel 3, Transfer Count register

00–15

Yes

0008

Channels 0–3, Read Status/Write Command register00–07

0009

Channels 0–3, Write Request register

00–02

000A

Channels 0–3, Write Single Mask

register bits 00–02

000B

Channels 0–3, Mode register (write)

00–07

000C

Channels 0–3, Clear byte pointer (write)

N/A

000D

Channels 0–3, Master clear (write)/temp (read)00–07

000E

Channels 0–3, Clear Mask register (write)

00–03

000F

Channels 0–3,

Write

All

Mask register bits

00–03

0081

Channel 2, Page Table Address 2register

00–07

0082

Channel 3, Page Table Address 2register

00–07

0083

Channel

1,

Page

Table

Address 2 register

00–07

0087

Channel

0,

Page

Table

Address

2

00–07

register

0089

Channel

6,

Page

Table

Address

2

00–07

register

008A

Channel

7,

Page

Table

Address

2

00–07

register

008B

2

00–07

Channel 5, Page Table Address register

008F

Channel 4, Page Table Address/Refresh register00–07

00C0

Channel 4, Memory Address register

00–15

Yes

00C2

Channel 4, Transfer Count register

00–15

Yes

00C4

Channel 5, Memory Address register

00–15

Yes

00C6

Channel 5, Transfer Count register

00–15

Yes

00C8

Channel

6,

Memory

Address register

00–15

Yes

38 Technical Information Manual