Appendix B. System address maps
Appendix | B. |
| System |
| address maps |
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System |
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The | first | 640 | KB | of | system | board | RAM is | mapped | starting | at | address |
| hex 0000000. A 256 b | ||||||||||||||||
a 1 KB area of this RAM are reserved for | BIOS | data | areas. Memory | can | be mapped | ||||||||||||||||||||||||
detects | an | error. |
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Figure | 35. |
| System memory map |
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Address | range (decimal) |
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| Address range | (hex) |
| Size |
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| Description |
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0 K | – | 512 | K |
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| 512 | KB |
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| Conventional |
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512 | K | – | 639 | K |
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| 127 | KB |
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| Extended | conventional |
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639 | K | – | 640 | K |
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| 1 | KB |
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| Extended | BIOS | data |
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640 | K | – | 767 | K |
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| 128 | KB |
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| Dynamic |
| video | memory |
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| display |
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768 | K | – | 800 | K |
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| C0000 | to | C7FFF |
| 32 | KB |
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| Video | ROM | BIOS |
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| (shadowed) |
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800 | K | – | 896 | K |
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| 96 KB |
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| PCI | space, | available | to | ||||||||
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| adapter | ROMs |
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896 | K | – | 1 MB |
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| 128 | KB |
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| System | ROM | BIOS | (main |
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| memory | shadowed) |
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1 | MB | – | 16 | MB |
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| 15 | MB |
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| PCI | space |
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16 | MB | – | 4095.872 | MB |
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| 4079.8 MB |
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| PCI | space | (positive | decode) | |||||||||||
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| FFFE0000 – | FFFFFFFF |
| 128 | KB |
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| System | ROM | BIOS |
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Input/output | address |
| map |
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The | following | figure | lists | resource | assignments | for |
| the | I/O | address | map. Any addresses | ||||||||||||||||||
shown | are | reserved. |
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Figure | 36 | (Page | 1 |
| of | 3). |
| I/O address map |
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Address | (Hex) |
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| 16 | bytes |
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| DMA | 1 |
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| 16 | bytes |
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| General I/O locations — available to PCI bus |
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| 2 | bytes |
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| Interrupt controller | 1 |
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| 30 | bytes |
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| General I/0 locations — available to PCI bus |
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| 4 | bytes |
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| Counter/timer | 1 |
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| 28 | bytes |
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| General I/0 locations — available to PCI bus |
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0060 |
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| 1 | byte |
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| Keyboard controller byte - reset IRQ |
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0061 |
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| 1 | byte |
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| PIIX4, | system | port | B |
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0064 |
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| 1 | byte |
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| Keyboard controller, | CMD/STAT | byte |
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0070, | bit | 7 |
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| 1 | bit |
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| Enable NMI |
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0070, | bits 6:0 |
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| 1 | bit |
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0071 |
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| 1 | byte |
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| 14 | bytes |
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| General | I/O | locations — | available | to | PCI bus |
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0080 |
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| 1 | byte |
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| POST checkpoint register during POST only |
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008F |
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| 1 | byte |
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| Refresh | page | register |
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36 | Copyright IBM Corp. September 1999 |