IBM PC 300PL manual Appendix A. Connector pin assignments, Monitor connector

Page 33

Appendix A. Connector pin assignments

Appendix A. Connector pin assignments

The following figures show the pin assignments for various system board connectors.

Monitor connector

51

10

6

15

11

Figure

15. Monitor port connector pin assignments—SVGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

 

Signal

 

 

 

I/O

 

 

Pin

 

Signal

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

Red

 

 

 

O

2

 

 

 

Green

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

Blue

 

 

 

O

4

 

 

 

Monitor ID 2 - Not

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

used

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

Ground

 

 

NA

6

 

 

 

 

 

Red

 

ground

 

NA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

Green

ground

NA

8

 

 

 

 

 

Blue

 

ground

 

NA

 

 

 

 

 

 

 

 

 

 

 

 

9

 

+5 V, used by DDC2BNA

10

 

 

 

Ground

 

 

NA

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

Monitor

ID

0 -

Not I

12

 

 

DDC2B

serial

data

I/O

 

 

used

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

Horizontal

sync

O

14

 

 

Vertical

sync

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

DDC2B

clock

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

C1

C2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C3

C4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure

16. Monitor port connector pin assignments—DVI main pin field

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

 

Signal

 

 

 

I/O

 

 

Pin

 

Signal

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

TMDS

data

2+

O

2

 

 

 

TMDS

data

2-

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

TMDS

data

2/4

return N/A

4

 

 

 

TMDS data 4-*

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

TMDS

data

4+*

O

6

 

 

 

 

 

DDC

clock

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

DDC

data

 

I/O

8

 

 

 

 

 

Analog

vertical

sync

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

TMDS

data

1-

O

10

 

 

 

TMDS

data

1+

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

TMDS

data

1/3

shieldN/A

12

 

 

TMDS

data

3+*

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

TMDS

data

3+*

O

14

 

 

+5V

 

power

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

Ground

 

 

N/A

16

 

 

 

Hot

 

plug

detect

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

 

TMDS

data

0-

O

18

 

 

 

TMDS

data

0+

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

Return

 

 

N/A

20

 

 

 

TMDS

D5*

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

TMDS

data

5+*

O

22

 

 

TMDS

clock

shield

N/A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

 

TMDS

clock+

 

O

24

 

 

TMDS

clock-

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Copyright IBM Corp. September 1999

25

Image 33
Contents Page Apply 1999Are WithContents Error codes BiosSystem software PostReferences Index Contents USB port Internal Dasd Recovery jumper Power-input requirementsRelated publications PrefaceTerminology usage ViiEquals Bytes, and2 073 824Expressing storage Capacity Equals Major features System overviewSystem overview POST/BIOS Other featuresNetwork support PCIOn Ring System board features FeaturesFeatures SystemRimm System memoryPCI bus IDE bus master interfaceUSB interface Bus Video subsystemList Bus Mastering Support For Fast Performance 64-bit 125 Interface Plug Play support Advanced PowerVideo subsystem resources Resource AssignmentFeatures Monitor supportAudio subsystem Diskette Drive interface Super input/output controllerSeria l ports PortKeyboard and mouse ports Network connectionRPL Flash Eeprom System board features Real-timeExpansion adapters Physical layoutRiser card layouts System board, Types 6584Cable connectors Recovery jumperRecovery jumper DVISystem board Connector panelThis Section Lists Physical Specifications For Physical specificationsTypes 6584 and 6594. NICRequirements For TowerWake LAN adapters Have Pin Right-angle Header For AUX5Power input Power supplyPower output Power supplyComponents draw less current than Maximum Shown Component outputsOutput protection Connector descriptionSystem software PlaySystem software Diagnostic program Flash update utility programConfiguration/Setup UtilityHardware compatibility System compatibilityHardware interrupts System compatibilitySoftware compatibility Hard disk drives and controllerSoftware interrupts Machine-sensitive programsMonitor connector Appendix A. Connector pin assignmentsAppendix A. Connector pin assignments Monitor port connector pin assignments-SVGASystem memory connector pin assignments Memory connectorsPin Signal Pin assignmentsPin Assignments PCI connector pin assignmentsPin ConnectorConnectors Are on Riser card Connector slot One Only For All Other slots, the signalThese Assignments Are For For pin A41IDE connector pin assignments IDE connectorsDiskette drive connector pin assignments ConnectorPower supply connector pin assignments Pin Signal nameTamper detection switch Alert on LAN connectorsConnector pin Radio frequency identification Rfid pin assignmentsUSB port connectors CD audio connectorPort KeyboardSerial port connector pin assignments Keyboard port connector pin assignmentsParallel port connector pin assignments ConnectorPin Signal Ground System Appendix B. System address mapsInput/output AppendixO address map MapsDMA I/O address map Are ReservedHex Size Description Bits Byte PointerConfiguration MapSystem address maps Appendix C. IRQ and DMA channel assignments Appendix C. IRQ and DMA channel assignmentsIRQ channel assignments DMA channel assignmentsAppendix D. Error Codes Appendix D. Error codesCodes Beep codesAppendix E. Notices and trademarks References This PublicationReference Advanced Power SpecificationReferences Connector IndexIndex Memory Features Wake on LAN 2 Wake on RingRfid