Quatech ES-100 user manual Fifo Control Register 16550 only, RXT0

FIFO CONTROL REGISTER (16550 only)

This register, which applies only to the 16550 UART, is a write-only register located at I/O address [base+2]. It is used to enable the FIFO mode, clear the FIFOs, set the threshold level for the receive FIFO to generate interrupts, and to set the mode under which the device uses DMA. Note that DMA mode is NOT supported by the ES-100D.

BIT			DESCRIPTION
7	RXT1 ---	Receiver FIFO Trigger Level (16550 only):
6	RXT0 ---	Determines the trigger level for the receiver FIFO interrupt
		RXT1	RXT0	Receiver FIFO trigger level (bytes)
		0	0	1
		0	1	4
		1	0	8
		1	1	14
5	0 --- reserved
4	0 --- reserved
3	DMAM --- DMA mode select (16550 only):
	When set (logic 1), RxRDY and TxRDY change from mode 0 to mode 1 for DMA transfers.
	(DMA mode is not supported on the ES-100D.)
2	XRST --- Transmit FIFO reset (16550 only):
	When set (logic 1), all bytes in the transmitter FIFO are cleared and the counter is reset. The
	shift register is not cleared. XRST is self-clearing.
1	RRST --- Receive FIFO reset (16550 only):
	When set (logic 1), all bytes in the receiver FIFO are cleared and the counter is reset. The
	shift register is not cleared. RRST is self-clearing.
0	FE --- FIFO enable (16550 only):
	When set (logic 1), enables transmitter and receiver FIFOs. When cleared (logic 0), all bytes
	in both FIFOs are cleared. This bit must be set when other bits in the FIFO control register
	are written to or the bits will be ignored.
	Figure 17 --- 16550 FIFO Control Register bit definitions

16 Quatech ES-100D User's Manual