Quatech ES-100 user manual Addressing Ports, Setting the address

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3.ADDRESSING PORTS

Setting the address

The base address of the ES-100D is set using the two DIP switch packs. When setting the address selection switches, a switch in the "ON" position specifies that the corresponding address line must be a logic 0 for the port to be selected. Similarly, a switch in the "OFF" position forces the corresponding address line to be a logic 1 for the port to be selected.

A full sixteen bit address decode is implemented to reduce the chance of address conflicts with other adapters in the system. The base address of the ES-100D can be set anywhere in the range of 0000 hex to FFFF hex. Each serial port on the ES-100D uses 8 consecutive I/O locations. The ports reside in a contiguous block of I/O space in eight byte increments, for a total of 64 contiguous bytes. This is shown in Figure 3.

PORT

ADDRESS RANGE

 

 

 

 

Serial 1

Base Address + 0

to

Base Address + 7

 

 

 

 

Serial 2

Base Address + 8

to

Base Address + 15

 

 

 

 

Serial 3

Base Address + 16

to

Base Address + 23

Serial 4

Base Address + 24

to

Base Address + 31

 

 

 

 

Serial 5

Base Address + 32

to

Base Address + 39

 

 

 

 

Serial 6

Base Address + 40

to

Base Address + 47

 

 

 

 

Serial 7

Base Address + 48

to

Base Address + 55

 

 

 

 

Serial 8

Base Address + 56

to

Base Address + 63

Figure 3 --- Port address map

Switch SW1 and the first four positions of switch SW2 select address lines A15 through A6. The fifth position of SW2 is not used. The remaining address lines, A5 - A0, are used by the UART to select the register being accessed.

The sixth position on SW2 is used to enable or disable the interrupt status register (see page 7).

Figure 4 shows how the switches on the ES-100D represent the address values for serial ports. This figure can be used to explain the examples shown in Figure 5.

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Quatech ES-100D User's Manual

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Contents ES-100 Page Warranty Information Page FCC Class B EC Council Directive 89/336/EECGeneral Information Port Address IRQ InstallationDiagram of ES-100D Addressing Ports Setting the addressExamination of a serial port base address Interrupt Level IRQ Interrupt SharingInterrupt Status register Interrupt Status Register contents This page intentionally left blank External Connections ES-100D connector definitions Channel Output ConfigurationES-100D output connectors Serial Port Functional Description Dlab Accessing the Serial Port registersInterrupt Identification Register Interrupt Enable RegisterInterrupt Identification Register bit definitions RXT0 Fifo Control Register 16550 onlyEPS PEN Parity Line Control RegisterModem Control Register bit definitions Modem Control RegisterLine Status Register bit definitions Line Status RegisterScratchpad Register Modem Status RegisterWhen the receiver Fifo and receiver interrupts are enabled Fifo Interrupt Mode Operation 16550 Uart onlyFifo polled mode operation 16550 Uart only Value Values % Baud Rate Selection16450 16550 optional SpecificationsComputer will not boot up TroubleshootingVersion March Quatech Inc, ES-100 Manual
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