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Programming the TMS320DM642
Note: The unscaled Decoder 2 displays in both Quadrant 2 and 3 since Decoder 2 takes priority over Decoder 3 when both are unscaled.
Table 11. Decoder 2 Register
Address | 01h |
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Default | 12h |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Capture
ReservedPositionCapture Size
Enable
Capture Size | Bit 2 | Bit 1 | Bit 0 | |
Unscaled | 0 | 0 | 0 | |
QSIF – 176 × 120 | 0 | 0 | 1 | |
SIF – 352 × 240 (1/4 NTSC) | 0 | 1 | 0 | |
(default) | ||||
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QCIF – 176 × 144 | 0 | 1 | 1 | |
CIF – 352 × 288 (1/4 PAL) | 1 | 0 | 0 | |
QVGA – 320 × 240 | 1 | 0 | 1 | |
VGA – 640 × 480 | 1 | 1 | 0 | |
Reserved | 1 | 1 | 1 | |
Capture Enable | Bit 3 |
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Disable (default) | 0 |
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Enable | 1 |
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Position | Bit 5 | Bit 4 |
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Quadrant 1 | 0 | 0 |
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Quadrant 2 (default) | 0 | 1 |
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Quadrant 3 | 1 | 0 |
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Quadrant 4 | 1 | 1 |
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Quad 1 | Quad 2 |
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Quad 3 | Quad 4 |
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SLEU069A | TVP5154EVM User's Guide | 29 |