Testing Procedure | Texas Instruments TPS62065 specification

www.ti.com

Test Configuration

5.2Testing Procedure

Follow these procedures when configuring the EVM for testing.

CAUTION

Many of the components on the TPS62065/67EVM-347 are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap, bootstraps, or mats at an approved ESD workstation. An electrostatic smock and safety glasses should also be worn.

1.Connect a dc power supply between J10 and J12 on the TPS62065EVM, or J20 and J22 on the TPS62067EVM. Please note that the input voltage should be between 3.0 V and 6.0 V. Keep the wires from the input power supply to the EVM as short as possible and twisted.

2.Connect a dc voltmeter or oscilloscope to the output sense connection of the EVM (J14 on the TPS62065EVM, J24 on the TPS62067EVM).

3.A load can be connected between J13 and J15 on the TPS62065EVM, or J23 and J25 on the TPS62067EVM.

4.To enable the converter, connect the shorting bar on JP10 (JP20) between EN and ON on the TPS62065EVM (TPS62067EVM).

5.The TPS62065EVM has a feature to allow the user to switch between Power-Save Mode under light loads and forced PWM mode; this feature is enabled or disabled with jumper JP11. This feature is only available on the TPS62065EVM.

6.The TPS62067EVM has a PG (Power Good) output. The PG pin on the TPS62067 is connected to J26. PG is an open-drain output. The output is pulled up with a 1-MΩ pull-up resistor (R22) to VIN. This feature is only available on the TPS62067EVM.

SLVU364 –March 2010	TPS62065/67EVM	7
Submit Documentation Feedback