4.2System Architecture
The
JTAG Header
SRAM
544KB Flash
(U4)
4M X 32bit
SDRAM (U5, U6)
USB Connector
FXUSBEZ |
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| External Bus Interface |
| SPI 1:0 |
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20MHz |
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| DSP |
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Oscillator |
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Crystal |
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32.768KHz |
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| RTC |
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Power | VDD_INT |
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Management |
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3.3V | VDD_EXT | ||||
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+7.5V Connector
5V A5V 3.3V
Power
Regulation
AD1885
Codec
(U7)
SPORT0
Connector
Stereo LINEIN/
MIC and
LINEOUT
Connectors
Figure 4-1: System Architecture
The DSP has a default core voltage of 1.5V. Refer to section 3.6.1 for more information about changing the core voltage while the DSP is running. The voltage of the DSP’s peripheral interface is 3.3V.
A 20 MHz oscillator supplies the input clock to the DSP. The speed at which the core and peripherals operate is determined by the configuration of the multiplier select switch (SW2) at reset. (See section 4.3.4.) By default, the DSP core runs at 300 MHz and the peripheral interface runs at 120 MHz. A 32.768 kHz crystal supplies the Real Time Clock (RTC) inputs of the DSP
The
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