Stereo LINE_IN (DEFAULT)
MIC | JP1LINE |
2 | 6 |
1 | 5 |
Mono MIC1
MIC | JP1LINE |
2 | 6 |
1 | 5 |
Figure 4-3: Audio Input Jumper Settings (JP1)
4.3.2Audio Codec Disable Jumper (JP2)
Placing a jumper between pins 1 and 2 of JP2 holds the AD1885 in reset, preventing it from driving signals to the serial port. When a jumper is between pins 2 and 3 of JP2, the AD1885 is held in reset until PF15 is set to an output and is asserted. These position are labeled on the board as “DIS” and “ENA 1885”.
4.3.3Boot Mode Select Switch (SW1)
The boot mode select switch determines how the DSP will boot. Table
NOTE: SPI ROM is not available on the
Table
|
|
BMODE0 | BMODE1 |
Pin 1 | Pin 2 |
BMODE2 Function Pin 3
On | On | On |
|
|
|
Off | On | On |
|
|
|
On | Off | On |
|
|
|
Off | Off | On |
|
|
|
- | - | Off |
Execute from 16 bit external memory (no boot)
Boot from 8-bit EPROM (Default)
Boot from SPI0 ROM
Boot from SPI0 ROM
All others reserved
4.3.4DSP PLL Setup Switch (SW2)
The DSP’s Phase Lock Loop (PLL) multiplies the 20 MHz input clock by a multiplication factor to set the core clock speed of the DSP. Internal to the DSP the Programmable Flags,
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