Analog Devices AD9883A manual SOG 0EH, Ahs, Avs

AD9883A

137-0 Post-Coast

This register allows the coast signal to be applied follow- ing to the Vsync signal. This is necessary in cases where post-equalization pulses are present. The step size for this control is one Hsync period.

The default is 0.

147 Hsync Detect

This bit is used to indicate when activity is detected on the Hsync input pin (Pin 30). If Hsync is held high or low, activity will not be detected.

Table XXVII. Hsync Detection Results

Detect	Function
0	No Activity Detected
1	Activity Detected

The sync processing block diagram shows where this function is implemented.

146 AHS – Active Hsync

This bit indicates which Hsync input source is being used by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1 in this register are what determine which source is used. If both Hsync and SOG are detected, the user can determine which has priority via Bit 3 in register 0EH. The user can override this function via Bit 4 in register 0EH. If the override bit is set to Logic 1, then this bit will be forced to whatever the state of Bit 3 in register 0EH is set to.

Table XXVIII. Active Hsync Results

Bit 7	Bit 1	Bit 4, Reg
(Hsync	(SOG	0EH
Detect)	Detect)	(Override)	AHS
0	0	0	Bit 3 in 0EH
0	1	0	1
1	0	0	0
1	1	0	Bit 3 in 0EH
X	X	1	Bit 3 in 0EH

AHS = 0 means use the Hsync pin input for Hsync. AHS = 1 means use the SOG pin input for Hsync.

The override bit is in register 0EH, Bit 4.

145 Detected Hsync Input Polarity Status

This bit reports the status of the Hsync input polarity detection circuit. It can be used to determine the polarity of the Hsync input. The detection circuit’s location is shown in the Sync Processing Block Diagram (Figure 12).

Table XXIX. Detected Hsync Input Polarity Status

Hsync Polarity Status	Result
0	Hsync Polarity Is Negative
1	Hsync Polarity Is Positive

144 Vsync Detect

This bit is used to indicate when activity is detected on the Vsync input pin (Pin 31). If Vsync is held high or low, activity will not be detected.

Table XXX. Vsync Detection Results

Detect Function

0No Activity Detected

1Activity Detected

The Sync Processing Block Diagram (Figure 12) shows where this function is implemented.

143 AVS – Active Vsync

This bit indicates which Vsync source is being used; the Vsync input or output from the sync separator. Bit 4 in this register determines which is active. If both Vsync and SOG are detected, the user can determine which has priority via Bit 0 in register 0EH. The user can override this function via Bit 1 in register 0EH. If the override bit is set to Logic 1, this bit will be forced to whatever the state of Bit 0 in register 0EH is set.

Table XXXI. Active Vsync Results

Bit 5
(Vsync Detect)	Override	AVS
0	0	0
1	0	1
X	1	Bit 0 in 0EH

AVS = 0 means Vsync input.

AVS = 1 means Sync separator.

The override bit is in register 0EH, Bit 1.

142 Detected Vsync Output Polarity Status

This bit reports the status of the Vsync output polarity detection circuit. It can be used to determine the polarity of the Vsync output. The detection circuit’s location is shown in the Sync Processing Block Diagram.

Table XXXII. Detected Vsync Output Polarity Status

Vsync Polarity Status	Result
0	Vsync Polarity Is Active Low
1	Vsync Polarity Is Active High

141 Sync-on-Green Detect

This bit is used to indicate when sync activity is detected on the Sync-on-Green input pin (Pin 49).

Table XXXIII. Sync-on-Green Detection Results

Detect	Function
0	No Activity Detected
1	Activity Detected

The sync processing block diagram shows where this function is implemented.

140 Detected COAST Polarity Status

This bit reports the status of the coast input polarity detection circuit. It can be used to determine the polarity of the coast input. The detection circuit’s location is shown in the Sync Processing Block Diagram (Figure 12).

REV. 0 –19–