Analog Devices AD9883A manual Resolution, DC Accuracy, Lsb, Analog Input, Reference Output, Msps

AD9883A–SPECIFICATIONS

Analog Interface (VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate unless otherwise noted.)

		Test		AD9883AKST-110			AD9883AKST-140
Parameter	Temp	Level	Min	Typ	Max	Min	Typ	Max	Unit
RESOLUTION				8			8		Bits
DC ACCURACY	25°C			± 0.5			± 0.5
Differential Nonlinearity		I			+1.25/–1.0			+1.35/–1.0	LSB
	Full	VI			+1.35/–1.0			+1.45/–1.0	LSB
Integral Nonlinearity	25°C	I		± 0.5	± 1.85		± 0.5	± 2.0	LSB
	Full	VI			± 2.0			± 2.3	LSB
No Missing Codes	Full	VI		Guaranteed			Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum	Full	VI			0.5			0.5	V p-p
Maximum	Full	VI	1.0			1.0			V p-p
Gain Tempco	25°C	V		100			100		ppm/°C
Input Bias Current	25°C	IV			1			1	∝A
	Full	IV			1			1	∝A
Input Offset Voltage	Full	VI		7	50		7	70	mV
Input Full-Scale Matching	Full	VI		1.5	6.0		1.5	8.0	% FS
Offset Adjustment Range	Full	VI	46	49	52	46	49	52	% FS
REFERENCE OUTPUT
Output Voltage	Full	VI	1.20	1.25	1.32	1.20	1.25	1.32	V
Temperature Coefficient	Full	V		± 50			± 50		ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate	Full	VI	110				140		MSPS
Minimum Conversion Rate	Full	IV			10			10	MSPS
Data to Clock Skew	Full	IV	–0.5		+2.0	–0.5		+2.0	ns
tBUFF	Full	VI	4.7			4.7			∝s
tSTAH	Full	VI	4.0			4.0			∝s
tDHO	Full	VI	0			0			∝s
tDAL	Full	VI	4.7			4.7			∝s
tDAH	Full	VI	4.0			4.0			∝s
tDSU	Full	VI	250			250			∝s
tSTASU	Full	VI	4.7			4.7			∝s
tSTOSU	Full	VI	4.0			4.0			∝s
HSYNC Input Frequency	Full	IV	15		110	15		110	kHz
Maximum PLL Clock Rate	Full	VI	110			140			MHz
Minimum PLL Clock Rate	Full	IV			12			12	MHz
PLL Jitter	25°C	IV		400	7001		400	7001	ps p-p
	Full	IV			10001			10001	ps p-p
Sampling Phase Tempco	Full	IV		15			15		ps/°C
DIGITAL INPUTS
Input Voltage, High (VIH)	Full	VI	2.5			2.5			V
Input Voltage, Low (VIL)	Full	VI			0.8			0.8	V
Input Voltage, High (VIH)	Full	V			–1.0			–1.0	∝A
Input Voltage, Low (VIL)	Full	V			+1.0			+1.0	∝A
Input Capacitance	25°C	V		3			3		pF

–2– REV. 0