AD9883A
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| OFFSET = 7Fh |
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| OFFSET = 3Fh |
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RANGE | 0.5 |
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| OFFSET = 7Fh | |
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| 0.0 | OFFSET = 3Fh |
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| OFFSET = 00h |
| 00h | FFh |
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| GAIN |
Figure 2. Gain and Offset Control
Gain and Offset Control
The AD9883A can accommodate input signals with inputs ranging from 0.5 V to 1.0 V full scale. The
Note that increasing the gain setting results in an image with less contrast.
The offset control shifts the entire input range, resulting in a change in image brightness. Three
The offset controls provide a ± 63 LSB adjustment range. This range is connected with the
Figure 2 illustrates the interaction of gain and offset controls. The magnitude of an LSB in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. The change is minimal if the offset setting in near midscale. When changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero scale level.
Sync-on-Green
The
47nF
RAIN
47nF
BAIN
47nF
GAIN
1nF
SOG
Figure 3. Typical Clamp Configuration
Clock Generation
A Phase Locked Loop (PLL) is employed to generate the pixel clock. In this PLL, the Hsync input provides a reference fre- quency. A Voltage Controlled Oscillator (VCO) generates a much higher pixel clock frequency. This pixel clock is divided by the PLL divide value (registers 01H and 02H) and phase compared with the Hsync input. Any error is used to shift the VCO frequency and maintain lock between the two signals.
The stability of this clock is a very important element in provid- ing the clearest and most stable image. During each pixel time, there is a period during which the signal is slewing from the old pixel amplitude and settling at its new value. Then there is a time when the input voltage is stable, before the signal must slew to a new value (Figure 4). The ratio of the slewing time to the stable time is a function of the bandwidth of the graphics DAC and the bandwidth of the transmission system (cable and termination). It is also a function of the overall pixel rate. Clearly, if the dynamic characteristics of the system remain fixed, then the slewing and settling time is likewise fixed. This time must be subtracted from the total pixel period, leaving the stable period. At higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well.
PIXEL CLOCK | INVALID SAMPLE TIMES | ||||||
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Figure 4. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the sampling time can be determined, and must also be subtracted from the stable pixel time.
Considerable care has been taken in the design of the AD9883A’s clock generation circuit to minimize jitter. As indicated in Fig- ure 5, the clock jitter of the AD9883A is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible.
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– % | 10 |
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JITTER | 8 |
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CLOCK | 6 |
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PIXEL |
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| 0 | 31.5 | 36.0 | 36.0 | 50.0 | 56.25 | 75.0 | 85.5 | 110.0 |
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FREQUENCY – MHz
Figure 5. Pixel Clock Jitter vs. Frequency
REV. 0 |