AD9883A
Table VI. Control Register Map (continued)
| Write and |
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Hex | Read or |
| Default | Register |
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Address | Read Only | Bits | Value | Name | Function | |
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15H | R/W | 7:0 |
| Test Register | Bits [7:2] Reserved for future use. | |
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| Bit 1 | – 4:2:2 Output Formatting Mode. |
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| Bit 0 | – Must be set to 0 for proper operation. |
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16H | R/W | 7:0 |
| Test Register | Reserved for future use. | |
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17H | RO | 7:0 |
| Test Register | Reserved for future use. | |
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18H | RO | 7:0 |
| Test Register | Reserved for future use. | |
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NOTE
1The AD9883A only updates the PLL divide ratio when the LSBs are written to (register 02h).
TWO-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
An
The AD9883A updates the full divide ratio only when this register is written to.
CLOCK GENERATOR CONTROL
03
Two bits that establish the operating range of the clock generator.
PLL DIVIDER CONTROL
017–0 PLL Divide Ratio MSBs
The eight most significant bits of the
The PLL derives a master clock from an incoming Hsync signal. The master clock frequency is then divided by an integer value, such that the output is
The
VESA has established some standard timing specifications, which will assist in determining the value for PLLDIV as a function of horizontal and vertical display resolution and frame rate (Table V).
However, many computer systems do not conform pre- cisely to the recommendations, and these numbers should be used only as a guide. The display system manufacturer should provide automatic or manual means for optimizing PLLDIV. An incorrectly set PLLDIV will usually produce one or more vertical noise bars on the display. The greater the error, the greater the number of bars produced.
The
The AD9883A updates the full divide ratio only when the LSBs are changed. Writing to the MSB by itself will not trigger an update.
027–4 PLL Divide Ratio LSBs
The four least significant bits of the
The
REV. 0
VCORNGE must be set to correspond with the desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high fre- quencies. For this reason, in order to output low pixel rates and still get good jitter performance, the PLL actu- ally operates at a higher frequency but then divides down the clock rate afterwards. Table VII shows the pixel rates for each VCO range setting. The PLL output divisor is automatically selected with the VCO range setting.
| Table VII. VCO Ranges | |
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VCORNGE |
| Pixel Rate Range |
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00 |
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01 |
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10 |
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10 |
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The power-up default value is 01.
03
Three bits that establish the current driving the loop filter in the clock generator.
Table VIII. Charge Pump Currents
CURRENT | Current (A) |
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000 | 50 |
001 | 100 |
010 | 150 |
011 | 250 |
100 | 350 |
101 | 500 |
110 | 750 |
111 | 1500 |
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CURRENT must be set to correspond with the desired operating frequency (incoming pixel rate).
The