
SBA-7222G-T2 Blade Module User’s Manual
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Post Code | Description | |
40h | Preparing the descriptor tables next. | |
42h | The descriptor tables are prepared. Entering protected mode for the | |
memory test next. | ||
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43h | Entered protected mode. Enabling interrupts for diagnostics mode next. | |
44h | Interrupts enabled if the diagnostics switch is on. Initializing data to check | |
memory wraparound at 0:0 next. | ||
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45h | Data initialized. Checking for memory wraparound at 0:0 and finding the | |
total system memory size next. | ||
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46h | The memory wraparound test is done. Memory size calculation has been | |
done. Writing patterns to test memory next. | ||
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47h | The memory pattern has been written to extended memory. Writing | |
patterns to the base 640 KB memory next. | ||
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48h | Patterns written in base memory. Determining the amount of memory | |
below 1 MB next. | ||
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49h | The amount of memory below 1 MB has been found and verified. | |
| The amount of memory above 1 MB has been found and verified. | |
4Bh | Checking for a soft reset and clearing the memory below 1 MB for the soft | |
| reset next. If this is a power on situation, going to checkpoint 4Eh next. | |
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4Ch | The memory below 1 MB has been cleared via a soft reset. Clearing the | |
memory above 1 MB next. | ||
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4Dh | The memory above 1 MB has been cleared via a soft reset. Saving the | |
memory size next. Going to checkpoint 52h next. | ||
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4Eh | The memory test started, but not as the result of a soft reset. Displaying | |
the first 64 KB memory size next. | ||
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4Fh | The memory size display has started. The display is updated during the | |
memory test. Performing the sequential and random memory test next. | ||
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50h | The memory below 1 MB has been tested and initialized. Adjusting the | |
displayed memory size for relocation and shadowing next. | ||
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51h | The memory size display was adjusted for relocation and shadowing. | |
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52h | The memory above 1 MB has been tested and initialized. Saving the | |
memory size information next. | ||
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53h | The memory size information and the CPU registers are saved. Entering | |
real mode next. | ||
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54h | Shutdown was successful. The CPU is in real mode. Disabling the Gate | |
A20 line, parity, and the NMI next. | ||
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57h | The A20 address line, parity, and the NMI are disabled. Adjusting the | |
memory size depending on relocation and shadowing next. | ||
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58h | The memory size was adjusted for relocation and shadowing. Clearing | |
the Hit <DEL> message next. | ||
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