SBA-7222G-T2 Blade Module User’s Manual
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Post Code | Description | |
FCh | Next, erasing the flash ROM. | |
FDh | Next, programming the flash ROM. | |
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FFh | Flash ROM programming was successful. Next, restarting the system | |
BIOS. | ||
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Uncompressed Initialization Codes
The following runtime checkpoint codes are listed in order of execution in Table
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Post Code | Description | |
03h | The NMI is disabled. Next, checking for a soft reset or a power on | |
condition. | ||
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05h | The BIOS stack has been built. Next, disabling cache memory. | |
06h | Uncompressing the POST code next. | |
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07h | Next, initializing the CPU and the CPU data area. | |
08h | The CMOS checksum calculation is done next. | |
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0Ah | The CMOS checksum calculation is done. Initializing the CMOS status | |
register for date and time next. | ||
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0Bh | The CMOS status register is initialized. Next, performing any required | |
initialization before the keyboard BAT command is issued. | ||
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0Ch | The keyboard controller input buffer is free. Next, issuing the BAT | |
command to the keyboard controller. | ||
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| The keyboard controller BAT command result has been verified. Next, | |
0Eh | performing any necessary initialization after the keyboard controller BAT | |
| command test. | |
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0Fh | The initialization after the keyboard controller BAT command test is done. | |
The keyboard command byte is written next. | ||
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10h | The keyboard controller command byte is written. Next, issuing the Pin 23 | |
and 24 blocking and unblocking command. | ||
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| Next, checking if <End or <Ins> keys were pressed during power on. | |
11h | Initializing CMOS RAM if the Initialize CMOS RAM in every boot | |
AMIBIOS POST option was set in AMIBCP or the <End> key was | ||
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| pressed. | |
12h | Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2. | |
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13h | The video display has been disabled. Port B has been initialized. Next, | |
initializing the chipset. | ||
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14h | The 8254 timer test will begin next. | |
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19h | Next, programming the flash ROM. | |
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