Feature | Option | Description | |
North Bridge Chipset Configuration |
| ||
Channel Dependent | Enabled | Channel dependent rank/DIMM sparing | |
Sparing | Disabled | enabled/disabled | |
|
| ||
|
|
| |
Channel 0 | Enabled | Channel 0 enabled/disabled | |
Disabled | |||
|
| ||
Channel Specific | Disabled | Enables rank/DIMM sparing feature | |
Sparing | Enabled | ||
| |||
|
| ||
Rank Interleaving | 1:1 | Rank Interleaving setting | |
2:1 | |||
| 4:1 |
| |
Channel 1 | Enabled | Channel 1 enabled/disabled | |
| |||
Disabled | |||
|
| ||
|
|
| |
Channel Specific | Disabled | Enables rank/DIMM sparing feature | |
Sparing | Enabled | ||
| |||
|
| ||
|
|
| |
Rank Interleaving | 1:1 | Rank Interleaving setting | |
2:1 | |||
| 4:1 |
| |
Boots Graphic Adapter | Auto | Select which graphic controller to use | |
Priority | Onboard VGA | as the primary boot device. | |
|
| ||
|
|
| |
Read Completion | Disabled |
| |
| Read returns of > 64B | ||
Enabled | |||
Coalescing | |||
|
| ||
| Auto |
| |
|
|
| |
| Auto | Auto: Dram Clock running by SPD | |
DRAM Clock |
| DDR533: Force memory running at 533 | |
| |||
| DDR533 | MHz | |
|
|
|
64