Nvidia 754 specifications Appendix

Appendix

43h	Test 8259 functionality.
44h	Reserved
45-46h	Reserved
47h	Initialize EISA slot
48h	Reserved
49h	1.	Calculate total memory by testing the last double word of each 64K
		page.
	2.	Program writes allocation for AMD K5 CPU.
4A-4Dh	Reserved
4Eh	1.	Program MTRR of M1 CPU
	2.	Initialize L2 cache for P6 class CPU & program CPU with proper
		cacheable range.
	3.	Initialize the APIC for P6 class CPU.
	4.	On MP platform, adjust the cacheable range to smaller one in case
		the cacheable ranges between each CPU are not identical.
4Fh	Reserved
50h	Initialize USB
51h	Reserved
52h	Test all memory (clear all extended memory to 0)
53-54h	Reserved
55h	Display number of processors (multi-processor platform)
56h	Reserved
57h	1.	Display PnP logo
	2.	Early ISA PnP initialization
		-Assign CSN to every ISA PnP device.
58h	Reserved
59h	Initialize the combined Trend Anti-Virus code.
5Ah	Reserved
5Bh	(Optional Feature) Show message for entering AWDFLASH.EXE
	from FDD (optional)
5Ch	Reserved
5Dh	1.	Initialize Init_Onboard_Super_IO switch.
	2.	Initialize Init_Onbaord_AUDIO switch.
5E-5Fh	Reserved
60h	Okay to enter Setup utility; i.e. not until this POST stage can users enter
	the CMOS setup utility.
61-64h	Reserved
65h	Initialize PS/2 Mouse
66h	Reserved
67h	Prepare memory size information for function call: INT 15h ax=E820h
68h	Reserved
69h	Turn on L2 cache
6Ah	Reserved
6Bh	Program chipset registers according to items described in Setup & Auto-
	configuration table.
6Ch	Reserved
6Dh	1.	Assign resources to all ISA PnP devices.
	2.	Auto assign ports to onboard COM ports if the corresponding item
		in Setup is set to “AUTO”.

C-3