Operational Description

The State Logic Processor (SLP) uses areas in the CPU memory for I/O references and Register values. The SLP and the CPU communicate this information over the PLC backplane.

When a Ladder Logic control program and a State Logic control program are running at the same time, the State Logic and Ladder Logic programs should not be controlling the same outputs. The SLP cannot control an output that is being controlled by the CPU, since the 90-30 CPU always takes precedence when both processors are controlling the same outputs.

All of the outputs used in the State Logic program should be selected to be contiguous if system response time is important. Outputs being non-contiguous causes the scan rate to increase significantly.

When changing outputs the SLP writes to a byte of I/O bits at a time, so that any the SLP actually controls eight ouputs at a time. Therefore, if some outputs of a byte are not named in the SLP program, ECLiPS issuses a warning that the other outputs in that byte are changed when the program executes.

1-4	State Logic Processor for Series 90±30 PLC User's Guide ± March 1998	GFK-0726B
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