Cypress CY2291 manual Features, Benefits, Logic Block Diagram

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CY2291

Three-PLL General Purpose EPROM Programmable Clock Generator

Features

Three integrated phase-locked loops

EPROM programmability

Factory-programmable (CY2291) or field-programmable (CY2291F) device options

Low-skew, low-jitter, high-accuracy outputs

Power-management options (Shutdown, OE, Suspend)

Frequency select option

Smooth slewing on CPUCLK

Configurable 3.3V or 5V operation

20-pin SOIC Package

Benefits

Generates up to three custom frequencies from external sources

Easy customization and fast turnaround

Programming support available for all opportunities

Meets critical industry standard timing requirements

Supports low-power applications

Eight user-selectable frequencies on CPU PLL

Allows downstream PLLs to stay locked on CPUCLK output

Enables application compatibility

Industry-standard packaging saves on board space

Part Number

Outputs

Input Frequency Range

Output Frequency Range

Specifics

CY2291

8

10 MHz–25 MHz (external crystal)

76.923 kHz–100 MHz (5V)

Factory Programmable

 

 

1 MHz–30 MHz (reference clock)

76.923 kHz–80 MHz (3.3V)

Commercial Temperature

CY2291I

8

10 MHz–25 MHz (external crystal)

76.923 kHz–90 MHz (5V)

Factory Programmable

 

 

1 MHz–30 MHz (reference clock)

76.923 kHz–66.6 MHz (3.3V)

Industrial Temperature

CY2291F

8

10 MHz–25 MHz (external crystal)

76.923 kHz–90 MHz (5V)

Field Programmable

 

 

1 MHz–30 MHz (reference clock)

76.923 kHz–66.6 MHz (3.3V)

Commercial Temperature

CY2291FI

8

10 MHz–25 MHz (external crystal)

76.923 kHz–80 MHz (5V)

Field Programmable

 

 

1 MHz–30 MHz (reference clock)

76.923 kHz–60.0 MHz (3.3V)

Industrial Temperature

Logic Block Diagram

32XIN

OSC.

 

 

32K

32XOUT

 

 

 

 

 

 

XTALIN

OSC.

 

 

XBUF

XTALOUT

 

 

CPLL

 

 

 

 

/1,2,4

 

CPUCLK

S0

(8 BIT)

 

 

 

 

 

S1

 

 

 

CLKA

S2/SUSPEND

UPLL

 

 

CLKB

 

/1,2,4,8

MUX

 

(10 BIT)

 

 

 

 

 

 

/1,2,3,4,5,6

CLKC

 

 

 

 

 

 

 

 

SPLL

/8,10,12,13

 

CLKD

 

/20,24,26,40

 

 

(8 BIT)

/48,52,96,104

 

 

 

 

/2,3,4

 

CLKF

 

 

 

CONFIG

 

SHUTDOWN/

 

 

EPROM

 

 

 

 

 

OE

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 38-07189 Rev. *C

 

Revised September 16, 2008

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Contents Logic Block Diagram FeaturesBenefits Cypress Semiconductor Corporation 198 Champion CourtPin Definitions Name Pin Number Description PinoutsPower Saving Features Output ConfigurationCustom Configuration Request Procedure OperationMaximum Ratings Electrical Characteristics, CommercialOperating Conditions5 Parameter Description Part Numbers Min Max UnitElectrical Characteristics, Industrial Parameter Name Description Min Typ Max Unit Switching Characteristics, CommercialCpll Operation 80 MHz 76.923 kHz CY2291F CY2291F MHz66.6 MHz 76.923 kHz Output Duty 50%Output Period Clock output range CY2291I Switching Characteristics, Industrial5V operation 90 MHz 76.923 kHz CY2291FI 80 MHz 76.923 kHz Output DutyMHz/ms Switching WaveformsClock Jitter14 Peak-to-peak period jitter Clock Jitter14 Peak-to-peak period jitter fOUT 50 MHzTest Circuit Package CharacteristicsOrdering Information Pin 300 MIL Soic Package Outline Package DiagramDocument History Sales, Solutions, and Legal InformationOrig. Submission Description of Change Date