Cypress STK14C88-5 manual Device Operation, Sram Read, Sram Write, AutoStore Operation

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STK14C88-5

Device Operation

The STK14C88-5 nvSRAM is made up of two functional compo- nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The STK14C88-5 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL opera- tions from the nonvolatile cells and up to one million STORE operations.

SRAM Read

The STK14C88-5 performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–14determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0–7are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.

AutoStore Operation

The STK14C88-5 stores data to nvSRAM using one of three storage operations:

1.Hardware store activated by HSB

2.Software store activated by an address sequence

3.AutoStore on device power down

having a capacitor of between 68uF and 220uF (+ 20%) rated at 6V should be provided. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up.

Figure 3. AutoStore Mode

In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 μF capacitor. In this mode, the AutoStore function of the STK14C88-5 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms STORE cycle.

To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored, unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.

If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 2.2 ohm resistor should be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP.

AutoStore Inhibit mode

AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK14C88-5.

During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor.

Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor

If an automatic STORE on power loss is not required, then VCC is tied to ground and + 5V is applied to VCAP (Figure 4). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK14C88-5 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control or the HSB pin. To enable or disable Autostore using an I/O port pin see “” on page 5. It is not permissible to change between these three options” on the fly”.

Document Number: 001-51038 Rev. **

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Contents San Jose, CA Document Number 001-51038 Rev Revised March 02 FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtPin Definitions Pin ConfigurationsSram Write AutoStore Inhibit modeDevice Operation Sram ReadSoftware Recall Hardware Recall Power UpHardware Store HSB Operation Software StoreHardware Protect Low Average Active PowerData Protection Noise ConsiderationsHardware Mode Selection A13-A0 Mode PowerBest Practices Data Retention and Endurance DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Conditions AC Switching Characteristics Switching WaveformsParameter Description 35 ns 45 ns Unit Cypress Alt Min Max Switching Parameter Alt Description STK14C88-5 Unit Min Max AutoStore or Power Up RecallParameter Alt Description 35 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Low to Store Busy 300 Hardware Store CycleHardware Store High to Inhibit Off 700 Hardware Store Pulse WidthOrdering Information Part Numbering Nomenclature STK14C88 5 C 35 MPin 300-Mil Side Braze DIL Package DiagramPad 450-Mil LCC Sales, Solutions, and Legal Information New data sheetDocument History

STK14C88-5 specifications

The Cypress STK14C88-5 is a high-performance, non-volatile static random-access memory (SRAM) solution that caters to a wide range of applications. This device seamlessly combines the benefits of SRAM technology with non-volatile memory, making it a compelling option for embedded systems requiring fast access speeds alongside persistent data storage.

One of the key features of the STK14C88-5 is its memory density. This chip comes with an 88 Kbit storage capacity, which is ample for various applications, including configuration storage and data logging in industrial systems, telecommunications, and consumer electronics. The memory is organized in a way that supports both byte-wise and word-wise access, ensuring flexibility to accommodate different data structures.

Speed is another attractive characteristic of the STK14C88-5. It operates at access speeds of up to 55 nanoseconds, providing quick read and write capabilities. This rapid performance is crucial for time-sensitive applications, enabling the device to handle real-time data processing effectively. The SRAM also supports a wide operating voltage range from 2.7V to 5.5V, making it versatile for different power supply configurations.

The device utilizes advanced technology to enhance reliability and endurance. The STK14C88-5 features built-in EEPROM technology, which allows it to retain data even when power is lost. This non-volatility is ideal for critical applications where data integrity is paramount.

In terms of interface, the STK14C88-5 provides a simple parallel interface, ensuring compatibility with various microcontrollers and processors. It also has control signals that support straightforward data read and write operations, allowing designers to integrate it easily into their existing architectures.

Moreover, the Cypress STK14C88-5 incorporates low-power consumption features, making it suitable for battery-operated devices. Its efficient power management ensures minimal energy usage without compromising performance, which is crucial in today’s energy-conscious environment.

Overall, the Cypress STK14C88-5 stands out with its combination of non-volatile storage, high-speed access, flexibility of operation, and power efficiency. These features make it an ideal choice for applications that demand reliable memory solutions with fast data processing capabilities, solidifying its position as a valuable component in the semiconductor industry.
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