Cypress STK14C88-5 manual Hardware Store HSB Operation, Hardware Recall Power Up, Software Store

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STK14C88-5

Figure 4. AutoStore Inhibit Mode

Hardware STORE (HSB) Operation

The STK14C88-5 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK14C88-5 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver.

SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK14C88-5 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH.

During any STORE operation, regardless of how it is initiated, the STK14C88-5 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK14C88-5 remains disabled until the HSB pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.

If the STK14C88-5 is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14C88-5 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ sequence is performed:

1.Read address 0x0E38, Valid READ

2.Read address 0x31C7, Valid READ

3.Read address 0x03E0, Valid READ

4.Read address 0x3C1F, Valid READ

5.Read address 0x303F, Valid READ

6.Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation.

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed:

1.Read address 0x0E38, Valid READ

2.Read address 0x31C7, Valid READ

3.Read address 0x03E0, Valid READ

4.Read address 0x3C1F, Valid READ

5.Read address 0x303F, Valid READ

6.Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.

Document Number: 001-51038 Rev. **

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number 001-51038 Rev Revised March 02Pin Configurations Pin DefinitionsAutoStore Inhibit mode Device OperationSram Read Sram WriteHardware Recall Power Up Hardware Store HSB OperationSoftware Store Software RecallLow Average Active Power Data ProtectionNoise Considerations Hardware ProtectA13-A0 Mode Power Hardware Mode SelectionBest Practices DC Electrical Characteristics Maximum RatingsOperating Range Data Retention and EnduranceThermal Resistance CapacitanceAC Test Conditions Switching Waveforms AC Switching CharacteristicsParameter Description 35 ns 45 ns Unit Cypress Alt Min Max Switching AutoStore or Power Up Recall Parameter Alt Description STK14C88-5 Unit Min MaxSoftware Controlled STORE/RECALL Cycle Parameter Alt Description 35 ns 45 ns Unit Min MaxHardware Store Cycle Hardware Store High to Inhibit Off 700Hardware Store Pulse Width Hardware Store Low to Store Busy 300Part Numbering Nomenclature STK14C88 5 C 35 M Ordering InformationPackage Diagram Pin 300-Mil Side Braze DILPad 450-Mil LCC New data sheet Sales, Solutions, and Legal InformationDocument History

STK14C88-5 specifications

The Cypress STK14C88-5 is a high-performance, non-volatile static random-access memory (SRAM) solution that caters to a wide range of applications. This device seamlessly combines the benefits of SRAM technology with non-volatile memory, making it a compelling option for embedded systems requiring fast access speeds alongside persistent data storage.

One of the key features of the STK14C88-5 is its memory density. This chip comes with an 88 Kbit storage capacity, which is ample for various applications, including configuration storage and data logging in industrial systems, telecommunications, and consumer electronics. The memory is organized in a way that supports both byte-wise and word-wise access, ensuring flexibility to accommodate different data structures.

Speed is another attractive characteristic of the STK14C88-5. It operates at access speeds of up to 55 nanoseconds, providing quick read and write capabilities. This rapid performance is crucial for time-sensitive applications, enabling the device to handle real-time data processing effectively. The SRAM also supports a wide operating voltage range from 2.7V to 5.5V, making it versatile for different power supply configurations.

The device utilizes advanced technology to enhance reliability and endurance. The STK14C88-5 features built-in EEPROM technology, which allows it to retain data even when power is lost. This non-volatility is ideal for critical applications where data integrity is paramount.

In terms of interface, the STK14C88-5 provides a simple parallel interface, ensuring compatibility with various microcontrollers and processors. It also has control signals that support straightforward data read and write operations, allowing designers to integrate it easily into their existing architectures.

Moreover, the Cypress STK14C88-5 incorporates low-power consumption features, making it suitable for battery-operated devices. Its efficient power management ensures minimal energy usage without compromising performance, which is crucial in today’s energy-conscious environment.

Overall, the Cypress STK14C88-5 stands out with its combination of non-volatile storage, high-speed access, flexibility of operation, and power efficiency. These features make it an ideal choice for applications that demand reliable memory solutions with fast data processing capabilities, solidifying its position as a valuable component in the semiconductor industry.
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