Cypress STK14C88-3 Pin Configurations, Write Enable Input, Active LOW . When the chip is enabled

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STK14C88-3

Pin Configurations

Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP

Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP

Pin Name

Alt

IO Type

 

 

Description

A0–A14

 

 

 

 

 

 

 

Input

Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

DQ0-DQ7

 

 

 

 

 

 

 

Input or

Bidirectional Data IO lines. Used as input or output lines depending on operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Write Enable Input, Active LOW. When the chip is enabled and

 

is LOW, data on the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

WE

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IO pins is written to the specific address location.

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

 

 

 

CE

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

chip.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Output Enable, Active LOW. The active LOW

 

input enables the data output buffers

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

OE

 

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

 

VSS

 

 

 

 

 

 

 

Ground

Ground for the Device. The device is connected to ground of the system.

 

VCC

 

 

 

 

 

 

 

Power Supply

Power Supply Inputs to the Device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input or

Hardware Store Busy

(HSB)

. When LOW, this output indicates a Hardware Store is in

 

HSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

weak internal pull up resistor keeps this pin high if not connected (connection optional).

VCAP

 

 

 

 

 

 

 

Power Supply

AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM to nonvolatile elements.

Document Number: 001-50592 Rev. **

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Contents Features Functional DescriptionOutput Enable, Active LOW . T he active LOW Pin ConfigurationsWrite Enable Input, Active LOW . When the chip is enabled Power Supply Inputs to the DeviceSram Read AutoStore Inhibit ModeDevice Operation Sram WriteSoftware Store Hardware Recall Power UpHardware Store HSB Operation Preventing Store Low Average Active PowerSoftware Recall Hardware ProtectBest Practices Hardware Mode Selection13 a Mode Power Maximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsParameter Description 35 ns 45 ns Unit Cypress Alt Min Max AC Switching CharacteristicsSwitching Waveforms Min Max Parameter Sram Write Cycle 1 WE Controlled 13AutoStore or Power Up Recall Parameter Alt Description STK14C88-3 Unit Min MaxSoftware Controlled STORE/RECALL Cycle Parameter Alt Description 35 ns 45 ns Unit Min MaxHardware Store Cycle Hardware Store CycleSTK14C88-3NF35ITR Part Numbering Nomenclature STK14C88- 3N F 45 I TROrdering Information STK14C88-3NF45ITRPackage Diagrams Pin 300 Mil SoicPin 600 Mil Pdip Document History Sales, Solutions and Legal InformationNew data sheet USB
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