Cypress STK14C88-3 manual Min Max Parameter, Sram Write Cycle 1 WE Controlled 13

STK14C88-3

Table 3. SRAM Write Cycle

	Parameter		Description		35 ns		45 ns		Unit
Cypress		Alt		Min		Max	Min	Max
Parameter
tWC		tAVAV	Write Cycle Time	35			45		ns
tPWE		tWLWH, tWLEH	Write Pulse Width	25			30		ns
tSCE		tELWH, tELEH	Chip Enable To End of Write	25			30		ns
tSD		tDVWH, tDVEH	Data Setup to End of Write	12			15		ns
tHD		tWHDX, tEHDX	Data Hold After End of Write	0			0		ns
tAW		tAVWH, tAVEH	Address Setup to End of Write	25			30		ns
tSA		tAVWL, tAVEL	Address Setup to Start of Write	0			0		ns
tHA		tWHAX, tEHAX	Address Hold After End of Write	0			0		ns
tHZWE [11,12]		tWLQZ	Write Enable to Output Disable			13		15	ns
tLZWE [11]		tWHQX	Output Active After End of Write	5			5		ns

Switching Waveforms

Figure 9. SRAM Write Cycle 1: WE Controlled [13, 14]

	tWC
ADDRESS
	tSCE
CE
	tAW
	tSA
WE	tPWE
	tSD
DATA IN	DATA VALID
	tHZWE
	HIGH IMPEDANCE

DATA OUT PREVIOUS DATA

tHA

tHD

tLZWE

Figure 10. SRAM Write Cycle 2: CE Controlled [13, 14]

ADDRESS

CE

WE

DATA IN

DATA OUT

tWC

tSA tSCE tHA

tAW

tPWE

tSD tHD

DATA VALID

HIGH IMPEDANCE

Notes

12.If WE is Low when CE goes Low, the outputs remain in the high impedance state.

13.CE or WE must be greater than VIH during address transitions.

14.HSB must be HIGH during SRAM WRITE cycles.

Document Number: 001-50592 Rev. ** Page 10 of 17

[+] Feedback