Cypress CY62138EV30 manual Read Cycle No OE Controlled14, Write Cycle No WE Controlled16

Page 6

CY62138EV30

MoBL®

Switching Waveforms (continued)

Read Cycle No. 2 (OE Controlled)[14, 15]

ADDRESS

 

 

 

CE

 

tRC

 

 

 

 

OE

tACE

 

 

 

 

 

 

tDOE

tHZOE

 

 

tLZOE

tHZCE

HIGH

DATA OUT

HIGH IMPEDANCE

DATA VALID

IMPEDANCE

 

 

 

tLZCE

tPD

 

VCC

tPU

 

 

ICC

SUPPLY

50%

 

50%

CURRENT

 

 

ISB

Write Cycle No. 1 (WE Controlled)[16, 18]

 

tWC

 

ADDRESS

 

 

CE

tSCE

 

 

 

 

tAW

tHA

tSA

tPWE

 

WE

 

 

OE

 

 

 

tSD

tHD

DATA I/O

 

 

 

 

 

 

 

 

 

 

 

DATAIN VALID

 

NOTE 17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHZOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

15.Address valid prior to or coincident with CE transition LOW.

16.Data I/O is high impedance if OE = VIH.

17.During this period, the I/Os are in output state and input signals should not be applied.

18.If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.

Document #: 38-05577 Rev. *A

Page 6 of 9

[+] Feedback

Image 6
Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor Corporation= 1 MHz = f max Min Typ Max Pin Configuration2Product Portfolio Typ MaxElectrical Characteristics Over the Operating Range Maximum RatingsAC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance Data Retention Waveform45 ns Parameter Description Unit Min Max Read Cycle Switching Characteristics Over the Operating Range9Switching Waveforms Write CycleRead Cycle No OE Controlled14 Write Cycle No WE Controlled16Write Cycle No CE Controlled16 Inputs/Outputs Mode PowerTruth Table Write Cycle No WE Controlled, OE LOW18Package Diagrams Ordering InformationBall Vfbga 6 x 8 x 1 mm Issue Orig. Description of Change Date Document History