Cypress CY62138EV30 Switching Characteristics Over the Operating Range9, Switching Waveforms

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CY62138EV30

MoBL®

Switching Characteristics (Over the Operating Range)[9]

 

 

 

 

 

 

 

 

45 ns

 

Parameter

 

 

 

 

 

Description

 

 

 

Unit

 

 

 

 

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRC

 

Read Cycle Time

45

 

 

ns

tAA

 

Address to Data Valid

 

 

45

ns

tOHA

 

Data Hold from Address Change

10

 

 

ns

tACE

 

 

 

 

 

LOW to Data Valid

 

 

45

ns

CE

 

tDOE

 

 

 

 

 

LOW to Data Valid

 

 

22

ns

OE

 

tLZOE

 

 

 

 

 

LOW to Low Z[10]

5

 

 

ns

OE

 

 

tHZOE

 

 

 

 

 

HIGH to High Z[10,11]

 

 

18

ns

OE

 

tLZCE

 

 

 

 

LOW to Low Z[10]

10

 

 

ns

CE

 

 

t

 

 

 

 

HIGH to High Z[10, 11]

 

 

18

ns

CE

 

HZCE

 

 

 

 

 

 

 

 

 

 

tPU

 

 

 

LOW to Power-up

0

 

 

ns

CE

 

 

tPD

 

 

 

 

HIGH to Power-up

 

 

45

ns

CE

 

Write Cycle[12]

 

 

 

 

 

 

 

 

 

 

tWC

 

Write Cycle Time

45

 

 

ns

tSCE

 

 

 

 

LOW to Write End

35

 

 

ns

CE

 

 

tAW

 

Address Set-up to Write End

35

 

 

ns

tHA

 

Address Hold from Write End

0

 

 

ns

tSA

 

Address Set-up to Write Start

0

 

 

ns

tPWE

 

 

 

 

 

Pulse Width

35

 

 

ns

WE

 

 

tSD

 

Data Set-up to Write End

25

 

 

ns

tHD

 

Data Hold from Write End

0

 

 

ns

t

 

 

 

 

 

LOW to High Z[10, 11]

 

 

18

ns

WE

 

HZWE

 

 

 

 

 

 

 

 

 

 

t

 

 

 

 

 

HIGH to Low Z[10]

10

 

 

ns

WE

 

 

LZWE

 

 

 

 

 

 

 

 

 

 

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[13, 14]

ADDRESS

tOHA

tRC

tAA

DATA OUT

PREVIOUS DATA VALID

Notes:

DATA VALID

9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.

10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high-impedance state.

12.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.

13.Device is continuously selected. OE, CE = VIL.

14.WE is HIGH for read cycle.

Document #: 38-05577 Rev. *A

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Contents Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationProduct Portfolio Pin Configuration2= 1 MHz = f max Min Typ Max Typ MaxMaximum Ratings Electrical Characteristics Over the Operating RangeThermal Resistance Data Retention Characteristics Over the Operating RangeAC Test Loads and Waveforms Data Retention WaveformSwitching Waveforms Switching Characteristics Over the Operating Range945 ns Parameter Description Unit Min Max Read Cycle Write CycleWrite Cycle No WE Controlled16 Read Cycle No OE Controlled14Truth Table Inputs/Outputs Mode PowerWrite Cycle No CE Controlled16 Write Cycle No WE Controlled, OE LOW18Ball Vfbga 6 x 8 x 1 mm Package DiagramsOrdering Information Document History Issue Orig. Description of Change Date