Cypress CY14B102L manual Hardware Recall Power Up, Software Store, Software Recall, Mode Selection

PRELIMINARY

CY14B102L, CY14B102N

completion of the STORE operation, the CY14B102L/CY14B102N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB will be driven LOW by the HSB driver.

Software STORE

Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B102L/CY14B102N software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following read sequence must be performed.

1.Read Address 0x4E38 Valid READ

2.Read Address 0xB1C7 Valid READ

3.Read Address 0x83E0 Valid READ

4.Read Address 0x7C1F Valid READ

5.Read Address 0x703F Valid READ

6.Read Address 0x8FC0 Initiate STORE Cycle

Table 1. Mode Selection

The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB will be driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.

Software RECALL

Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed.

1.Read Address 0x4E38 Valid READ

2.Read Address 0xB1C7 Valid READ

3.Read Address 0x83E0 Valid READ

4.Read Address 0x7C1F Valid READ

5.Read Address 0x703F Valid READ

6.Read Address 0x4C63 Initiate RECALL Cycle

Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.

					[3]	A15 - A0[8]	Mode	IO	Power
CE	WE	OE,	BHE,	BLE
H	X		X			X	Not Selected	Output High Z	Standby
L	H		L			X	Read SRAM	Output Data	Active
L	L		X			X	Write SRAM	Input Data	Active
L	H		L			0x4E38	Read SRAM	Output Data	Active[9, 10]
						0xB1C7	Read SRAM	Output Data
						0x83E0	Read SRAM	Output Data
						0x7C1F	Read SRAM	Output Data
						0x703F	Read SRAM	Output Data
						0x8B45	AutoStore	Output Data
							Disable

Notes

8.While there are 18 address lines on the CY14B102L (17 address lines on the CY14B102N), only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are don’t care.

9.The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.

10.IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.

Document #: 001-45754 Rev. *B Page 5 of 24

[+] Feedback