Cypress nvSRAM AutoStore/Power Up Recall, Parameters Description 20 ns 25 ns 45 ns Unit Min Max

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PRELIMINARY

CY14B102L, CY14B102N

AutoStore/Power Up RECALL

Parameters

 

 

Description

20 ns

 

 

25 ns

 

45 ns

Unit

 

 

Min

 

Max

Min

 

Max

Min

 

Max

 

 

 

 

 

 

 

 

 

t

[21]

 

Power Up RECALL Duration

 

 

20

 

 

20

 

 

20

ms

HRECALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSTORE [22]

 

STORE Cycle Duration

 

 

8

 

 

8

 

 

8

ms

tDELAY [23]

 

Time Allowed to Complete SRAM Cycle

 

 

20

 

 

25

 

 

25

ns

VSWITCH

 

 

Low Voltage Trigger Level

 

 

2.65

 

 

2.65

 

 

2.65

V

tVCCRISE

 

 

VCC Rise Time

150

 

 

150

 

 

150

 

 

μs

VHDIS[14]

 

 

HSB

Output Driver Disable Voltage

 

 

1.9

 

 

1.9

 

 

1.9

V

tLZHSB

 

 

HSB

To Output Active Time

 

 

5

 

 

5

 

 

5

μs

tHHHD

 

 

HSB

High Active Time

 

 

500

 

 

500

 

 

500

ns

Switching Waveforms

Figure 11. AutoStore or Power Up RECALL[24]

96:,7&+

 

 

 

 

 

 

 

 

 

9+',6

 

 

 

 

 

 

 

 

 

99&&5,6(

 

1RWH

W

6725(

 

 

 

1RWH

W

 

 

 

 

 

 

 

 

6725(

 

W+++'

 

 

 

W+++'

 

 

1RWH

 

 

 

 

 

 

 

+6%287

 

 

 

 

 

 

W'(/$<

 

 

 

 

 

 

 

 

 

 

 

$XWRVWRUH

W/=+6%

 

 

 

W

/=+6%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W'(/$<

 

 

 

 

 

 

 

32:(5

 

 

 

 

 

 

 

 

 

83

 

 

 

 

 

 

 

 

 

5(&$//

W+5(&$//

 

 

 

W+5(&$//

 

 

 

 

 

 

 

 

 

 

 

5HDG :ULWH

 

 

 

 

 

 

 

 

 

,QKLELWHG

 

 

 

 

 

 

 

 

 

5:,

5HDG :ULWH

 

 

 

 

5HDG

:ULWH

 

 

32:(583

%52:1

32:(583

 

32:(5

5(&$//

 

287

 

5(&$//

 

 

 

'2:1

 

 

 

$XWRVWRUH

 

 

 

$XWRVWRUH

Notes

21.tHRECALL starts from the time VCC rises above VSWITCH.

22.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.

23.On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.

24.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

25.HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Document #: 001-45754 Rev. *B

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor CorporationPinouts Top ViewNot to scale Pin Definitions Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A08 Mode Power Software StoreMode Selection A15 A08 Power Preventing AutoStoreData Protection Noise ConsiderationsDC Electrical Characteristics Maximum RatingsOperating Range Data Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsMin Max Sram Read Cycle$GGUHVV $GGUHVV9DOLG +LJK,PSHGDQFH6WDQGE\ $FWLYH Sram Write Cycle #2 CE Controlled3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxHSB Software Controlled STORE/RECALL Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthInputs/Outputs2 Mode Power Truth Table For Sram OperationsHigh Z Ordering Information CY14B102L-ZS25XCT CY14B102L-ZS25XITCY14B102L-ZS25XAT CY14B102N-BA25XCTCY14B102L-ZS45XCT CY14B102L-ZS45XITCY14B102L-ZS45XAT CY14B102L-BA45XCTPart Numbering Nomenclature CY 14 B 102 L ZS P 20 X C TZS Tsop NvsramPackage Diagrams TOP ViewBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Document History GvchGVCH/AESA GVCH/PYRSSales, Solutions, and Legal Information USB

CY14B102L, nvSRAM specifications

Cypress nvSRAM CY14B102L is a sophisticated memory solution designed to bridge the gap between volatile and non-volatile memory technologies. This device offers a unique blend of SRAM speed with the non-volatility of Flash memory, making it an ideal choice for applications that require data retention without the need for continuous power.

One of the standout features of the CY14B102L is its ability to retain data for over 20 years without power, thanks to its innovative non-volatile SRAM technology. This means that critical information can be stored safely during power outages or system failures, ensuring data integrity in mission-critical applications. The device uses a reliable, self-timed write process, which simplifies the write operation and enhances system efficiency by eliminating the need for complex write management processes.

With a capacity of 1 megabit (128 K x 8), the CY14B102L offers ample storage for a wide variety of applications. Its fast access times, typically around 45 ns, make it suitable for high-speed operations typically associated with SRAMs. This rapid access is paramount for real-time applications where delays can lead to critical failures or data corruption.

The CY14B102L utilizes a CMOS process technology that not only contributes to its low power consumption but also ensures high reliability and durability. Operating in the wide temperature range of -40°C to +125°C, this nvSRAM is well-suited for automotive, industrial, and telecommunications applications.

In terms of connectivity, the CY14B102L supports a standard SRAM interface, simplifying integration into existing systems. Additionally, its ease of use is further enhanced by being available in a variety of package options, allowing designers to select the best fit for their needs without compromising on performance.

In conclusion, the Cypress nvSRAM CY14B102L is a powerful memory device that combines the speed of SRAM with non-volatile storage capabilities. With its extended data retention, fast access times, efficient write processes, and robust design, it is an excellent choice for applications that demand both speed and reliability, making it an invaluable asset for engineers looking to optimize system performance while maintaining data integrity.