Cypress CY7C1218H Interleaved Burst Address Table Mode = Floating or VDD, Next Cycle Add. Used

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CY7C1218H

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1, A0

A1, A0

A1, A0

A1, A0

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

ZZ Mode Electrical Characteristics

Linear Burst Address Table (MODE = GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1, A0

A1, A0

A1, A0

A1, A0

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

Parameter

 

 

Description

 

 

 

 

 

 

Test Conditions

 

 

Min.

 

Max.

Unit

IDDZZ

Sleep mode standby current

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

40

 

mA

tZZS

Device operation to ZZ

 

 

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

2tCYC

ns

tZZREC

ZZ recovery time

 

 

 

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

2tCYC

 

 

ns

tZZI

ZZ Active to sleep current

 

 

 

 

 

This parameter is sampled

 

 

 

 

 

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

 

 

 

This parameter is sampled

 

 

0

 

 

 

ns

Truth Table[2, 3, 4, 5, 6, 7]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Next Cycle

 

Add. Used

ZZ

 

CE

1

CE2

 

CE

3

 

ADSP

 

 

ADSC

 

 

ADV

 

 

OE

 

 

DQ

 

Write

Unselected

 

None

L

 

H

X

 

X

 

X

 

 

L

 

X

 

X

 

 

Tri-State

 

X

Unselected

 

None

L

 

L

X

 

H

 

L

 

 

X

 

X

 

X

 

 

Tri-State

 

X

Unselected

 

None

L

 

L

L

 

X

 

L

 

 

X

 

X

 

X

 

 

Tri-State

 

X

Unselected

 

None

L

 

L

X

 

H

 

H

 

 

L

 

X

 

X

 

 

Tri-State

 

X

Unselected

 

None

L

 

L

L

 

X

 

H

 

 

L

 

X

 

X

 

 

Tri-State

 

X

Begin Read

 

External

L

 

L

H

 

L

 

L

 

 

X

 

X

 

X

 

 

Tri-State

 

X

Begin Read

 

External

L

 

L

H

 

L

 

H

 

 

L

 

X

 

X

 

 

Tri-State

 

Read

Continue Read

 

Next

L

 

X

X

 

X

 

H

 

 

H

 

L

 

H

 

 

Tri-State

 

Read

Continue Read

 

Next

L

 

X

X

 

X

 

H

 

 

H

 

L

 

L

 

 

DQ

 

Read

Continue Read

 

Next

L

 

H

X

 

X

 

X

 

 

H

 

L

 

H

 

 

Tri-State

 

Read

Continue Read

 

Next

L

 

H

X

 

X

 

X

 

 

H

 

L

 

L

 

 

DQ

 

Read

Suspend Read

 

Current

L

 

X

X

 

X

 

H

 

 

H

 

H

 

H

 

 

Tri-State

 

Read

Suspend Read

 

Current

L

 

X

X

 

X

 

H

 

 

H

 

H

 

L

 

 

DQ

 

Read

Suspend Read

 

Current

L

 

H

X

 

X

 

X

 

 

H

 

H

 

H

 

 

Tri-State

 

Read

Suspend Read

 

Current

L

 

H

X

 

X

 

X

 

 

H

 

H

 

L

 

 

DQ

 

Read

Begin Write

 

Current

L

 

X

X

 

X

 

H

 

 

H

 

H

 

X

 

 

Tri-State

 

Write

Begin Write

 

Current

L

 

H

X

 

X

 

X

 

 

H

 

H

 

X

 

 

Tri-State

 

Write

Begin Write

 

External

L

 

L

H

 

L

 

H

 

 

H

 

X

 

X

 

 

Tri-State

 

Write

Notes:

2.X = “Don't Care.” H = HIGH, L = LOW.

3.WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,BWB,BWC,BWD), BWE, GW = H.

4.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5.CE1, CE2, and CE3 are available only in the TQFP package.

6.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a don't care for the remainder of the Write cycle.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05667 Rev. *B

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Contents Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationSelection Guide Pin Configuration Pin TqfpCY7C1218H 166 MHz 133 MHz UnitPin Definitions Burst Sequences Sleep ModeFunctional Overview First Second Third Fourth Address A1, A0 Interleaved Burst Address Table Mode = Floating or VDDNext Cycle Add. Used WriteFunction Truth Table for Read/Write 2Operating Range Maximum RatingsAmbient Range Description Test Conditions Min Max UnitAC Test Loads and Waveforms Capacitance10Thermal Resistance Switching Characteristics Over the Operating Range 11 Read Cycle Timing17 Switching WaveformsADV Write Cycle Timing17CLZ Read/Write Cycle Timing17, 19DON’T Care ZZ Mode Timing21Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramDocument History Issue Date Orig. Description of Change

CY7C1218H specifications

The Cypress CY7C1218H is a high-performance synchronous static random-access memory (SRAM) device designed to meet the demanding requirements of advanced memory applications. This SRAM boasts a density of 2 Mbits, making it suitable for a variety of uses, including telecommunications, industrial, and consumer electronics.

One of the main features of the CY7C1218H is its fast access time, which ranges from 10 ns to 15 ns, depending on the specific configuration. This high-speed access allows for efficient read/write operations and ensures that the memory can keep pace with the needs of high-speed processors and data buses. The device operates with a single 3.3V supply, enhancing its compatibility with modern digital circuits and reducing power consumption.

The CY7C1218H employs a synchronous interface that simplifies the control signaling process and increases data transfer rates. This synchronous nature means that the operation of the chip is synchronized with an external clock, facilitating faster and more reliable data transfer between the memory and the host system. This is particularly beneficial in high-performance applications where latency and throughput are critical.

In addition to its speed and efficiency, the CY7C1218H features a low standby power mode. This is an essential characteristic for battery-powered and energy-efficient systems, as it significantly reduces power consumption when the device is not actively in use. The SRAM design also includes a write protect feature, enhancing data integrity and security in sensitive applications.

The device is packaged in a 44-pin TSOP (Thin Small Outline Package) and has a compact footprint, making it suitable for space-constrained designs. The CY7C1218H uses advanced CMOS technology to support reliable performance and long data retention, ensuring that stored data remains intact even during power-down cycles.

Overall, the Cypress CY7C1218H represents a robust solution for engineers looking to integrate high-speed, low-power SRAM into their designs. Its blend of speed, reliability, and efficiency makes it an excellent choice for applications requiring fast access and secure data storage, making it a staple in various electronic systems across different industries.
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