Cypress CY7C1218H manual Pin Definitions

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Pin Definitions

 

 

 

 

 

 

CY7C1218H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

I/O

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

A0, A1, A

Input-

Address Inputs used

to select one of the 32K address locations. Sampled at the rising edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

feed the 2-bit counter.

 

 

 

 

 

 

 

A,

 

 

 

B

Input-

Byte Write Select Inputs, active LOW. Qualified with

 

to conduct Byte Writes to the SRAM.

 

 

BW

BW

BWE

 

 

BWC, BWD

Synchronous

Sampled on the rising edge of CLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

 

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

Write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).

 

 

 

 

 

 

 

 

 

 

 

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

 

 

BWE

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted LOW to conduct a Byte Write.

 

 

 

 

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

counter when ADV is asserted LOW, during a burst operation.

 

 

 

 

 

1

 

 

 

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when a new external address is loaded.

 

 

 

 

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

loaded.

 

 

 

 

 

3

 

 

 

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

assumed active throughout this document for BGA. CE3 is sampled only when a new external

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address is loaded.

 

 

 

 

 

 

 

 

 

 

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as

 

 

 

 

 

 

 

 

 

 

 

 

 

 

input data pins. OE is masked during the first clock of a Read cycle when emerging from a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

deselected state.

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

 

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

automatically increments the address in a burst cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

 

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is deasserted HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

 

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When ADSP and ADSC are both asserted, only ADSP is recognized.

 

 

 

 

ZZ

Input-

ZZ “Sleep” Input, active HIGH. This input, when High places the device in a non-time-critical

 

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left

 

 

 

 

 

 

 

 

 

 

 

 

 

 

floating. ZZ pin has an internal pull-down.

 

 

 

 

DQA, DQB

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by

 

 

DQC, DQD

Synchronous

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

 

 

 

 

 

 

 

 

 

 

 

 

 

 

by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled by

 

 

DQPA,

 

OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are

 

 

DQPB

 

placed in a tri-state condition.

 

 

 

 

VDD

Power Supply

Power supply inputs to the core of the device.

 

 

 

 

VSS

Ground

Ground for the core of the device.

 

 

 

 

VDDQ

I/O Power

Power supply for the I/O circuitry.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Supply

 

 

 

 

 

 

 

 

 

 

VSSQ

I/O Ground

Ground for the I/O circuitry.

 

 

 

 

MODE

Input-

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left

 

 

 

 

 

 

 

 

 

 

 

 

 

Static

floating selects interleaved burst sequence. This is a strap pin and should remain static during

 

 

 

 

 

 

 

 

 

 

 

 

 

 

device operation. Mode Pin has an internal pull-up.

 

 

 

 

NC

 

No Connects. Not internally connected to the die. 2M, 4M, 9M,18M, 72M, 144M, 288M, 576M and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1G are address expansion pins and are not internally connected to the die.

 

 

Document #: 38-05667 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1166 MHz 133 MHz Unit Pin Configuration Pin TqfpSelection Guide CY7C1218HPin Definitions Sleep Mode Functional OverviewBurst Sequences Write Interleaved Burst Address Table Mode = Floating or VDDFirst Second Third Fourth Address A1, A0 Next Cycle Add. UsedFunction Truth Table for Read/Write 2Description Test Conditions Min Max Unit Maximum RatingsOperating Range Ambient RangeCapacitance10 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Read Cycle Timing17 Switching WaveformsADV Write Cycle Timing17CLZ Read/Write Cycle Timing17, 19DON’T Care ZZ Mode Timing21Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramDocument History Issue Date Orig. Description of Change

CY7C1218H specifications

The Cypress CY7C1218H is a high-performance synchronous static random-access memory (SRAM) device designed to meet the demanding requirements of advanced memory applications. This SRAM boasts a density of 2 Mbits, making it suitable for a variety of uses, including telecommunications, industrial, and consumer electronics.

One of the main features of the CY7C1218H is its fast access time, which ranges from 10 ns to 15 ns, depending on the specific configuration. This high-speed access allows for efficient read/write operations and ensures that the memory can keep pace with the needs of high-speed processors and data buses. The device operates with a single 3.3V supply, enhancing its compatibility with modern digital circuits and reducing power consumption.

The CY7C1218H employs a synchronous interface that simplifies the control signaling process and increases data transfer rates. This synchronous nature means that the operation of the chip is synchronized with an external clock, facilitating faster and more reliable data transfer between the memory and the host system. This is particularly beneficial in high-performance applications where latency and throughput are critical.

In addition to its speed and efficiency, the CY7C1218H features a low standby power mode. This is an essential characteristic for battery-powered and energy-efficient systems, as it significantly reduces power consumption when the device is not actively in use. The SRAM design also includes a write protect feature, enhancing data integrity and security in sensitive applications.

The device is packaged in a 44-pin TSOP (Thin Small Outline Package) and has a compact footprint, making it suitable for space-constrained designs. The CY7C1218H uses advanced CMOS technology to support reliable performance and long data retention, ensuring that stored data remains intact even during power-down cycles.

Overall, the Cypress CY7C1218H represents a robust solution for engineers looking to integrate high-speed, low-power SRAM into their designs. Its blend of speed, reliability, and efficiency makes it an excellent choice for applications requiring fast access and secure data storage, making it a staple in various electronic systems across different industries.
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