Cypress CY7C1218H manual Features, Functional Description1, Logic Block Diagram

CY7C1218H

1-Mbit (32K x36) Pipelined Sync SRAM

Features

•Registered inputs and outputs for pipelined operation

•32K × 36 common I/O architecture

•3.3V core power supply (VDD)

•2.5V/3.3V I/O power supply (VDDQ)

•Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

•Provide high-performance 3-1-1-1 access rate

•User-selectable burst counter supporting Intel→

Pentium interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•Available in JEDEC-standard lead-free 100-Pin TQFP package

•“ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1218H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1218H operates from a +3.3V core power supply while all outputs may operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram
A0, A1, A	ADDRESS
	REGISTER		2	A[1:0]
MODE
ADV				Q1
CLK			BURST
		COUNTER
		CLR	AND	Q0
ADSC			LOGIC
ADSP
	DQD,DQD			DQD ,DQPD
BWD	BYTE			BYTE
	WRITE REGISTER			WRITE DRIVER
	DQC,DQPC			DQC ,DQPC					DQs
BWC	BYTE			BYTE
								OUTPUT	DQPA
	WRITE REGISTER			WRITE DRIVER	MEMORY	SENSE	OUTPUT
								BUFFERS
					ARRAY		REGISTERS		DQPB
				DQB,DQPB		AMPS		E
	DQB,DQPB								DQPC
				BYTE
BWB	BYTE								DQPD
				WRITE DRIVER
	WRITE REGISTER
	DQA ,DQPA			DQA,DQPA
				BYTE
BWA	BYTE
				WRITE DRIVER
BWE	WRITE REGISTER
GW									INPUT
	ENABLE	PIPELINED							REGISTERS
CE1	REGISTER
		ENABLE
CE2
CE3
OE
ZZ	SLEEP
	CONTROL
Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05667 Rev. *B		Revised July 6, 2006

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