Cypress CY7C1223H manual Features, Selection Guide, MHz 133 MHz Unit

CY7C1223H

2-Mbit (128K x 18) Pipelined DCD Sync SRAM

Features Functional Description[1]

•Registered inputs and outputs for pipelined operation

•Optimal for performance (Double-Cycle deselect)

—Depth expansion without wait state

•128K × 18-bit common I/O architecture

•3.3V core power supply

•3.3V/2.5V I/O supply

•Fast clock-to-output time

—3.5 ns (for 166-MHz device)

—4.0 ns (for 133-MHz device)

•Provide high-performance 3-1-1-1 access rate

•User-selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous Output Enable

•Offered in JEDEC-standard lead-free 100-pin TQFP package

•“ZZ” Sleep Mode option

Selection Guide

The CY7C1223H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B] and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penal- izing system performance.

The CY7C1223H operates from a +3.3V core power supply while all outputs operate with either a +3.3V/2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

	166 MHz	133 MHz	Unit
Maximum Access Time	3.5	4.0	ns
Maximum Operating Current	240	225	mA
Maximum CMOS Standby Current	40	40	mA
Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05674 Rev. *B		Revised February 6, 2006

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