Cypress CY7C1223H manual Document History, Issue Date Orig. Description of Change

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CY7C1223H

Document History Page

Document Title: CY7C1223H 2-Mbit (128K x 18) Pipelined DCD Sync SRAM

Document Number: 38-05674

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	347357	See ECN	PCI	New Data Sheet

*A	424820	See ECN	RXU	Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Changed Three-State to Tri-State.
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table.
				Modified test condition from VIH < VDD to VIH < VDD
				Replaced Package Name column with Package Diagram in the Ordering
				Information table.
				Replaced Package Diagram of 51-85050 from A to B
*B	459347	See ECN	NXR	Converted from Preliminary to Final
				Included 2.5V I/O option
				Updated the Ordering Information table.

Document #: 38-05674 Rev. *B

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Contents Features Selection Guide166 MHz 133 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram OutputCY7C1223H Pin ConfigurationsTop View Pin Descriptions Functional Overview Sleep ModeBurst Sequences A1, A0 Adsp Adsc ADV Write CLKFunction ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Electrical Characteristics Over the Operating Range7 Maximum RatingsOperating Range Ambient RangeCapacitance9 Thermal Characteristics9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 14 Switching Waveforms Read Timing16Write Timing16 UndefinedRead/Write Timing16, 18 Adsp AdscZZ Mode Timing 20,21 DON’T CareOrdering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document History