Cypress CY7C1223H manual Switching Waveforms, Read Timing16

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CY7C1223H

Switching Waveforms

Read Timing[16]

tCYC

CLK

tCH

tADS tADH

tCL

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS

GW, BWE,BW[A:B]

CE

A1

tCES tCEH

	A2	A3
	tWES tWEH	Burst continued with
	tWES tWEH	new base address
		new base address
		Deselect
		cycle
	tADVS	tADVH

ADV
OE
	t	tOEHZ
	CLZ
Data Out (Q)	High-Z	Q(A1)
	tCO
	Single READ

ADV suspends burst

tOEV	tCO
tOELZ	tDOH						tCHZ
	Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)	Q(A3)
					Burst wraps around
			BURST READ		to its initial state
			BURST READ
	DON’T CARE		UNDEFINED

Note:

16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05674 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 166 MHz 133 MHz UnitOutput Logic Block DiagramTop View Pin ConfigurationsCY7C1223H Pin Descriptions Burst Sequences Sleep ModeFunctional Overview Adsp Adsc ADV Write CLK A1, A0Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsFunction Ambient Range Electrical Characteristics Over the Operating Range7Maximum Ratings Operating RangeAC Test Loads and Waveforms Thermal Characteristics9Capacitance9 Switching Characteristics Over the Operating Range 14 Read Timing16 Switching WaveformsUndefined Write Timing16Adsp Adsc Read/Write Timing16, 18DON’T Care ZZ Mode Timing 20,21Pin Tqfp 14 x 20 x 1.4 mm Package DiagramOrdering Information Document History Issue Date Orig. Description of Change