Cypress CY7C1223H manual Logic Block Diagram, Output

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							CY7C1223H
Logic Block Diagram
A0,A1,A	ADDRESS
A0,A1,A	REGISTER
	REGISTER
MODE		2	A[1:0]
MODE
ADV		BURST	Q1
CLK		BURST
CLK	COUNTER AND
	COUNTER AND
		LOGIC
	CLR		Q0
ADSC
ADSP
	DQB, DQPB		DQB , DQPB
	DQB, DQPB		BYTE
BWB	BYTE		WRITE DRIVER			OUTPUT	OUTPUT	DQs
BWB	WRITE REGISTER				SENSE	OUTPUT	OUTPUT	DQs
	WRITE REGISTER			MEMORY	SENSE	REGISTERS	BUFFERS	DQPA
				MEMORY	AMPS	REGISTERS	BUFFERS	DQPA
	DQA , DQPA		DQA, DQPA	ARRAY			E	DQPB
	DQA , DQPA		DQA, DQPA				E	DQPB
BWA	BYTE		BYTE
	BYTE		WRITE DRIVER
	WRITE REGISTER		WRITE DRIVER
BWE	WRITE REGISTER
BWE								INPUT
GW								INPUT
GW	ENABLE							REGISTERS
CE1	ENABLE	PIPELINED						REGISTERS
CE1	REGISTER	PIPELINED
CE2			ENABLE
CE3			ENABLE
CE3
OE
ZZ	SLEEP
ZZ	CONTROL
	CONTROL

Document #: 38-05674 Rev. *B

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Contents 166 MHz 133 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram OutputTop View Pin ConfigurationsCY7C1223H Pin Descriptions Burst Sequences Sleep ModeFunctional Overview A1, A0 Adsp Adsc ADV Write CLKParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsFunction Operating Range Electrical Characteristics Over the Operating Range7Maximum Ratings Ambient RangeAC Test Loads and Waveforms Thermal Characteristics9Capacitance9 Switching Characteristics Over the Operating Range 14 Switching Waveforms Read Timing16Write Timing16 UndefinedRead/Write Timing16, 18 Adsp AdscZZ Mode Timing 20,21 DON’T CarePin Tqfp 14 x 20 x 1.4 mm Package DiagramOrdering Information Issue Date Orig. Description of Change Document History