Cypress CY7C1916CV18, CY7C1318CV18, CY7C1320CV18 manual Switching Characteristics, Parameter Min Max

Page 23

CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

Switching Characteristics

Over the Operating Range [20, 21]

 

Cypress

Consortium

 

 

 

 

 

 

Description

267 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

POWER

 

V (Typical) to the First Access [22]

1

–

1

–

1

–

1

–

ms

 

 

DD

 

 

 

 

 

 

 

 

 

tCYC

tKHKH

K Clock and C Clock Cycle Time

3.75

8.4

4.0

8.4

5.0

8.4

6.0

8.4

ns

tKH

tKHKL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) HIGH

1.5

–

1.6

–

2.0

–

2.4

–

ns

tKL

tKLKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) LOW

1.5

–

1.6

–

2.0

–

2.4

–

ns

tKHKH

tKHKH

K Clock Rise to

 

 

Clock Rise and C to

 

 

 

Rise

1.68

–

1.8

–

2.2

–

2.7

–

ns

K

C

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKHCH

tKHCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/K

Clock Rise to C/C Clock Rise

0.00

1.68

0.00

1.8

0.00

2.2

0.00

2.7

ns

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tAVKH

Address Setup to K Clock Rise

0.3

–

0.5

–

0.6

–

0.7

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.5

–

0.6

–

0.7

–

ns

(LD,

R/W)

tSCDDR

tIVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.35

–

0.4

–

0.5

–

ns

Double Data Rate Control Setup to Clock (K/K)

 

 

 

 

 

Rise (BWS0, BWS1, BWS2, BWS3)

 

 

 

 

 

 

 

 

 

tSD [23]

tDVKH

D[X:0] Setup to Clock (K and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.35

–

0.4

–

0.5

–

ns

K) Rise

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

tKHAX

Address Hold after K Clock Rise

0.3

–

0.5

–

0.6

–

0.7

–

ns

tHC

tKHIX

Control Hold after K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.5

–

0.6

–

0.7

–

ns

(LD,

R/W)

tHCDDR

tKHIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

–

0.35

–

0.4

–

0.5

–

ns

Double Data Rate Control Hold after Clock (K/K)

 

 

 

Rise (BWS0, BWS1, BWS2, BWS3)

 

 

 

 

 

 

 

 

 

tHD

tKHDX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D[X:0] Hold after Clock (K/K)

Rise

0.3

–

0.35

–

0.4

–

0.5

–

ns

Notes

21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

22.This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.

23.For DQ2 data signal on CY7C1916CV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, and 267 MHz frequencies.

Document Number: 001-07160 Rev. *E

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1316CV18Logic Block Diagram CY7C1916CV18 DoffBWS Logic Block Diagram CY7C1318CV18Logic Block Diagram CY7C1320CV18 CY7C1916CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1316CV18 2M xCY7C1320CV18 512K x CY7C1318CV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview SRAM#2 Application ExampleEcho Clocks SRAM#1 ZQComments Write Cycle DescriptionsOperation First Address External Second Address InternalBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsDLL Timing Parameter Min Max Output TimesDON’T Care Undefined Switching WaveformsOrdering Information 200 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information

CY7C1320CV18, CY7C1916CV18, CY7C1316CV18, CY7C1318CV18 specifications

Cypress Semiconductor, a leading provider of high-performance memory solutions, offers a range of Static Random-Access Memory (SRAM) products ideal for various applications. Among these are the CY7C1320CV18, CY7C1916CV18, CY7C1316CV18, and CY7C1318CV18, each designed to meet the demands of modern electronic systems with distinctive features, technologies, and characteristics.

The CY7C1320CV18 is a high-performance 2-Mbit SRAM that operates at a voltage of 1.8V. Designed with speed in mind, it has access times as low as 12 ns, making it suitable for applications requiring quick data retrieval. The device features a simple asynchronous interface, allowing it to be easily integrated into various circuits. With a low power consumption profile and the ability to operate under a wide temperature range, the CY7C1320CV18 is an ideal choice for battery-operated devices and industrial environments.

Following closely, the CY7C1916CV18 is a highly integrated, 16-Mbit synchronous SRAM. This device stands out due to its robust data transfer capabilities, supporting a single-cycle read and write operation, which greatly enhances system performance. The device operates with a supply voltage of 1.8V and features an impressive latency, making it perfect for high-speed applications such as digital signal processing and telecommunications. The unique pipelined architecture allows for higher throughput and efficiency in memory access.

The CY7C1316CV18 is another notable member of this family, featuring 16K x 8 bits of memory. It is characterized by low power consumption and a fast access time, which helps to reduce latency in critical applications. With a simple asynchronous interface and competitive pricing, the CY7C1316CV18 is suitable for consumer electronics and automotive applications that require reliable performance.

Lastly, the CY7C1318CV18 is a comprehensive solution featuring 32K x 8 bits of memory. This device also operates with low power and high speed, making it efficient for caching, buffering, and temporary storage applications. Its compatibility with industry standards makes it easily integrable into existing systems.

In summary, the CY7C1320CV18, CY7C1916CV18, CY7C1316CV18, and CY7C1318CV18 SRAM devices from Cypress Semiconductor showcase cutting-edge technology, high performance, and versatility, catering to the evolving needs of today's electronics, from telecommunications to consumer devices. Their low power consumption, high-speed access, and reliable data integrity make them essential components in modern electronic designs.
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