Cypress CY7C1320CV18, CY7C1318CV18, CY7C1316CV18 manual Switching Waveforms, DON’T Care Undefined

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CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [27, 28, 29]

NOP

 

READ

READ

1

 

2

3

K

 

 

 

tKH

tKL

tCYC

tKHKH

K

 

 

 

LD

tSC

 

 

 

tHC

 

R/W

 

 

 

NOP

NOP

WRITE

WRITE

READ

 

 

 

4

5

6

7

8

9

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A0

A1

tSA

 

tHA

DQ

tKHCH tCLZ tCO

C

A2

A3

tHD

tSD

Q00 Q01 Q10

Q11

tCQDOH

 

tDOH

tCHZ

tCQD

 

A4

tHD

tSD

D21

D30

D31

Q41

t KHCH

C#

tKH tKL

 

tCYC

tKHKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ

tCQOH

tCCQO

tCQOH

CQ#

tCCQO

tCQH

 

tCQHCQH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DON’T CARE

UNDEFINED

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-07160 Rev. *E

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1916CV18 Logic Block Diagram CY7C1316CV18Doff CLKLogic Block Diagram CY7C1320CV18 Logic Block Diagram CY7C1318CV18BWS Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1316CV18 2M x CY7C1916CV18 2M xCY7C1320CV18 512K x CY7C1318CV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSRAM#1 ZQ SRAM#2Operation Write Cycle DescriptionsFirst Address External Second Address Internal CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsDLL Timing Parameter Min Max Output TimesDON’T Care Undefined Switching WaveformsOrdering Information 200 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information

CY7C1320CV18, CY7C1916CV18, CY7C1316CV18, CY7C1318CV18 specifications

Cypress Semiconductor, a leading provider of high-performance memory solutions, offers a range of Static Random-Access Memory (SRAM) products ideal for various applications. Among these are the CY7C1320CV18, CY7C1916CV18, CY7C1316CV18, and CY7C1318CV18, each designed to meet the demands of modern electronic systems with distinctive features, technologies, and characteristics.

The CY7C1320CV18 is a high-performance 2-Mbit SRAM that operates at a voltage of 1.8V. Designed with speed in mind, it has access times as low as 12 ns, making it suitable for applications requiring quick data retrieval. The device features a simple asynchronous interface, allowing it to be easily integrated into various circuits. With a low power consumption profile and the ability to operate under a wide temperature range, the CY7C1320CV18 is an ideal choice for battery-operated devices and industrial environments.

Following closely, the CY7C1916CV18 is a highly integrated, 16-Mbit synchronous SRAM. This device stands out due to its robust data transfer capabilities, supporting a single-cycle read and write operation, which greatly enhances system performance. The device operates with a supply voltage of 1.8V and features an impressive latency, making it perfect for high-speed applications such as digital signal processing and telecommunications. The unique pipelined architecture allows for higher throughput and efficiency in memory access.

The CY7C1316CV18 is another notable member of this family, featuring 16K x 8 bits of memory. It is characterized by low power consumption and a fast access time, which helps to reduce latency in critical applications. With a simple asynchronous interface and competitive pricing, the CY7C1316CV18 is suitable for consumer electronics and automotive applications that require reliable performance.

Lastly, the CY7C1318CV18 is a comprehensive solution featuring 32K x 8 bits of memory. This device also operates with low power and high speed, making it efficient for caching, buffering, and temporary storage applications. Its compatibility with industry standards makes it easily integrable into existing systems.

In summary, the CY7C1320CV18, CY7C1916CV18, CY7C1316CV18, and CY7C1318CV18 SRAM devices from Cypress Semiconductor showcase cutting-edge technology, high performance, and versatility, catering to the evolving needs of today's electronics, from telecommunications to consumer devices. Their low power consumption, high-speed access, and reliable data integrity make them essential components in modern electronic designs.