Cypress CY7C1333H Document History, Issue Date Orig. Description of Change 347377, New Datasheet

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PRELIMINARYCY7C1333H

Document History Page

Document Title: CY7C1333H 2-Mbit (64K x 32) Flow-Through SRAM with NoBL™ Architecture

Document Number: 001-00209

Document #: 001-00209 Rev. **

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Contents Features Logic Block DiagramFunctional Description1 Cypress Semiconductor CorporationPin Configurations Selection GuideCY7C1333H CY7C1333H-133 CY7C1333H-100 UnitMode Input. Selects the burst order of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Name DescriptionFunctional Overview Linear Burst Address Table Mode = GND First Second Third Fourth Address A1, A0First Second Third Fourth Address Parameter Description Test Conditions Min Max UnitTruth Table for Read/Write 2 FunctionMaximum Ratings Operating RangeThermal Resistance11 Switching Characteristics Over the Operating Range 12 CapacitanceAC Test Loads and Waveforms Switching Waveforms Address Hold after CLK RiseAD Hold after CLK Rise Read/Write Waveforms 18, 19ZZ Mode Timing22 Ordering InformationNOP, Stall and Deselect Cycles18, 19 Package Diagram Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Issue Date Orig. Description of Change 347377 New DatasheetDocument History