Cypress CY7C1333H manual Features, Functional Description1, Logic Block Diagram

PRELIMINARYCY7C1333H

2-Mbit (64K x 32) Flow-Through SRAM with NoBL™ Architecture

Features

•Can support up to 133-MHz bus operations with zero wait states.

—Data is transferred on every clock.

•Pin compatible and functionally equivalent to ZBT™ devices

•Internally self-timed output buffer control to eliminate the need to use OE

•Registered inputs for flow-through operation

•Byte Write capability

•64K x 32 common I/O architecture

•Single 3.3V power supply

•Fast clock-to-output times

—6.5 ns (for 133-MHz device)

—8.0 ns (for 100-MHz device)

•Clock Enable (CEN) pin to suspend operation

•Synchronous self-timed writes Offered in Lead-Free

•Asynchronous Output Enable

•Offered in Lead-Free JEDEC-standard 100 TQFP package

•Burst Capability—linear or interleaved burst order

• Low standby power

Functional Description[1]

The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1333H is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by the two Byte Write Select (BW[A:D]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

ADDRESS

A1

REGISTER

A1'

D1

Q1

MODE

A0

D0

Q0

A0'

CE

ADV/LD

BURST

CLK

C

LOGIC

CEN

C

WRITE ADDRESS

REGISTER

O

U

T

S

D

P

A

U

E

T

T

ADV/LD

N

A

BWA

MEMORY

S

B

WRITE REGISTRY

WRITE

ARRAY

E

S

U

DQs

BWB

AND DATA COHERENCY

DRIVERS

A

T

F

BWC

CONTROL LOGIC

E

F

M

E

E

BWD

P

R

R

S

I

S

WE

E

N

G

INPUT

E

REGISTER

OE

READ LOGIC

CE1

CE2

CE3

SLEEP

ZZ

Control

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	3901 North First Street	•	San Jose, CA 95134	•	408-943-2600
Document #: 001-00209 Rev. **					Revised April 11, 2005

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