Cypress CY7C1333H manual Name Description, Byte Write Inputs, active LOW . Qualified with

PRELIMINARY

CY7C1333H

Pin Definitions (100-pin TQFP Package)

Name

I/O

Description

A0, A1, A

Input-

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge

Synchronous

of the CLK. A[1:0] are fed to the two-bit burst counter.

BW

[A:D]

Input-

Byte Write Inputs, active LOW. Qualified with

WE

to conduct Writes to the SRAM. Sampled on

Synchronous

the rising edge of CLK.

WE

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if

CEN

is active LOW. This

Synchronous

signal must be asserted LOW to initiate a Write sequence.

Input-

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When

ADV/LD

Synchronous

HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new

address can be loaded into the device for an access. After being deselected, ADV/LD should be

driven LOW in order to load a new address.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

CEN.

CLK

is only recognized if CEN is active LOW.

1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

Synchronous

CE2, and CE3 to select/deselect the device.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous

CE1 and CE3 to select/deselect the device.

3

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

Synchronous

CE1 and CE2 to select/deselect the device.

Input-

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block

OE

Asynchronous

inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to

behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins.

OE is masked during the data portion of a Write sequence, during the first clock when emerging

from a deselected state, when the device has been deselected.

Input-

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the

CEN

Synchronous

SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

ZZ

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous

with data integrity preserved. During normal operation, this pin can be connected to VSS or left

floating.

DQs

I/O-

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered

Synchronous

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by address during the clock rise of the Read cycle. The direction of the pins is controlled

by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.

When HIGH, DQs are placed in a three-state condition. The outputs are automatically three-stated

during the data portion of a Write sequence, during the first clock when emerging from a deselected

state, and when the device is deselected, regardless of the state of OE.

Mode

Input

Mode Input. Selects the burst order of the device.

Strap Pin

When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved

burst sequence.

VDD

Power Supply

Power supply inputs to the core of the device.

VDDQ

I/O Power

Power supply for the I/O circuitry.

Supply

VSS

Ground

Ground for the device.

NC

–

No Connects. Not Internally connected to the die.

4M, 9M,18M,36M, 72M, 144M, 256M, 576M and 1G are address expansion pins and are not

internally connected to the die.

Document #: 001-00209 Rev. ** Page 3 of 12

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