Cypress CY7C1338G 133 100 Parameter Description Unit Min Max, Clock, Output Times, Setup Times

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CY7C1338G

Switching Characteristics Over the Operating Range [11, 12, 13, 14, 15, 16]

 

 

 

 

 

 

 

 

 

 

 

 

 

–133

–100

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

tPOWER

 

VDD(Typical) to the first Access[11]

1

 

1

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

7.5

 

10

 

ns

tCH

 

Clock HIGH

2.5

 

4.0

 

ns

tCL

 

Clock LOW

2.5

 

4.0

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCDV

 

Data Output Valid After CLK Rise

 

6.5

 

8.0

ns

tDOH

 

Data Output Hold After CLK Rise

2.0

 

2.0

 

ns

tCLZ

 

Clock to Low-Z[12, 13, 14]

0

 

0

 

ns

tCHZ

 

Clock to High-Z[12, 13, 14]

 

3.5

 

3.5

ns

tOEV

 

 

 

LOW to Output Valid

 

3.5

 

3.5

ns

OE

tOELZ

 

 

 

LOW to Output Low-Z[12, 13, 14]

0

 

0

 

ns

OE

tOEHZ

 

 

 

HIGH to Output High-Z[12, 13, 14]

 

3.5

 

3.5

ns

OE

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Set-up Before CLK Rise

1.5

 

2.0

 

ns

tADS

 

 

 

 

 

 

 

 

 

 

Set-up Before CLK Rise

1.5

 

2.0

 

ns

ADSP,

ADSC

tADVS

 

 

 

 

 

Set-up Before CLK Rise

1.5

 

2.0

 

ns

ADV

tWES

 

 

 

 

 

 

 

 

 

 

X Set-up Before CLK Rise

1.5

 

2.0

 

ns

GW,

BWE,

BW

tDS

 

Data Input Set-up Before CLK Rise

1.5

 

1.5

 

ns

tCES

 

Chip Enable Set-up

1.5

 

2.0

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.5

 

0.5

 

ns

tADH

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.5

 

0.5

 

ns

ADSP,

ADSC

tWEH

 

 

 

 

 

 

 

 

 

 

X Hold After CLK Rise

0.5

 

0.5

 

ns

GW,

BWE,

BW

tADVH

 

 

 

 

Hold After CLK Rise

0.5

 

0.5

 

ns

ADV

tDH

 

Data Input Hold After CLK Rise

0.5

 

0.5

 

ns

tCEH

 

Chip Enable Hold After CLK Rise

0.5

 

0.5

 

ns

Notes:

11.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.

12.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

13.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

14.This parameter is sampled and not 100% tested.

15.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05521 Rev. *D

Page 10 of 17

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Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor Corporation15CY7C1338G Pin ConfigurationsSelection Guide 133 MHz 100 MHz UnitName Description Pin Configurations Ball BGA PinoutPin Definitions Byte Write Select Inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Cycle Description Used CE2 Adsp Adsc ADV Write CLKPartial Truth Table for Read/Write2 FunctionAmbient Range Maximum RatingsOperating Range GND ≤ VI ≤ VddqThermal Resistance10 Capacitance10AC Test Loads and Waveforms Clock Setup Times133 100 Parameter Description Unit Min Max Output TimesTiming Diagrams Read Cycle Timing17Write Cycle Timing17 AdscRead/Write Timing17, 19 DON’T CareZZ Mode Timing 21 Ordering Information Package DiagramsPin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Issue Date Orig. Description of Change Document History