Cypress CY7C1338G manual Write Cycle Timing17, Adsc

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CY7C1338G

Timing Diagrams (continued)

Write Cycle Timing[17, 18]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst

BWE,

BW[A:D]

t t

WES WEH

ADSC extends burst

tADS tADH

tWES tWEH

tCES tCEH

tADVS tADVH

ADV

Data in (D)

High-Z

Data Out (Q)

tOEHZ

tDS t DH

D(A1)

ADV suspends burst

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST READ Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Document #: 38-05521 Rev. *D

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Contents Features Logic Block DiagramFunctional Description1 Cypress Semiconductor CorporationPin Configurations Selection Guide15CY7C1338G 133 MHz 100 MHz UnitPin Configurations Ball BGA Pinout Pin DefinitionsName Description Byte Write Select Inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Address Cycle Description Used CE2 Adsp Adsc ADV Write CLKPartial Truth Table for Read/Write2 FunctionMaximum Ratings Operating RangeAmbient Range GND ≤ VI ≤ VddqCapacitance10 Thermal Resistance10AC Test Loads and Waveforms Setup Times 133 100 Parameter Description Unit Min MaxClock Output TimesTiming Diagrams Read Cycle Timing17Write Cycle Timing17 AdscRead/Write Timing17, 19 DON’T CareZZ Mode Timing 21 Package Diagrams Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Issue Date Orig. Description of Change Document History