Cypress CY7C1338G manual Functional Overview

				CY7C1338G
Pin Definitions (continued)
	Name	I/O		Description
		Input-	Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
	ADSP
		Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
			also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
			nized. ASDP is ignored when CE1 is deasserted HIGH
		Input-	Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
	ADSC
		Synchronous	LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
			into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
	ZZ	Input-	ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
		Asynchronous	condition with data integrity preserved. During normal operation, this pin has to be low or left floating.
			ZZ pin has an internal pull-down.
	DQs	I/O-	Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
		Synchronous	the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
			by the addresses presented during the previous clock rise of the read cycle. The direction of the
			pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
			are placed in a tri-state condition.
	VDD	Power	Power supply inputs to the core of the device.
		Supply
	VSS	Ground	Ground for the core of the device.
	VDDQ	I/O Power	Power supply for the I/O circuitry.
		Supply
	VSSQ	I/O Ground	Ground for the I/O circuitry.
	MODE	Input-	Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
		Static	floating selects interleaved burst sequence. This is a strap pin and should remain static during device
			operation. Mode Pin has an internal pull-up.
	NC		No Connects. Not Internally connected to the die.
	NC/9M,	–	No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
	NC/18M		NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
	NC/36M		the die.
	NC/72M,
	NC/144M,
	NC/288M,
	NC/576M,
	NC/1G

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tC0) is 6.5 ns (133-MHz device).

The CY7C1338G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.

Document #: 38-05521 Rev. *D Page 4 of 17