Cypress CY62146E MoBL Maximum Ratings, Electrical Characteristics, Operating Range, Capacitance

CY62146E MoBL→

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature	–65°C to +150°C
Ambient Temperature with
Power Applied	–55°C to +125°C
Supply Voltage to Ground Potential	–0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State [3, 4]	–0.5V to 6.0V

Electrical Characteristics

Over the Operating Range

DC Input Voltage [3, 4]		–0.5V to 6.0V
Output Current into Outputs (LOW)			20 mA
Static Discharge Voltage			>2001V
(MIL-STD-883, Method 3015)
Latch up Current			>200 mA
Operating Range
Device	Range	Ambient	VCC	[5]
		Temperature
CY62146ELL	Ind’l/Auto-A	–40°C to +85°C	4.5V–5.5V

45 ns (Ind’l/Auto-A)

Parameter

Description

Test Conditions

Min

Typ [2]

Max

Unit

VOH

Output HIGH Voltage

IOH = –1.0 mA

2.4

V

VOL

Output LOW Voltage

IOL = 2.1 mA

0.4

V

VIH

Input HIGH Voltage

4.5 < VCC < 5.5

2.2

VCC + 0.5

V

VIL

Input LOW Voltage

4.5 < VCC < 5.5

–0.5

0.8

V

IIX

Input Leakage Current

GND < VI < VCC

–1

+1

μA

IOZ

Output Leakage Current

GND < VO < VCC, Output Disabled

–1

+1

μA

ICC

VCC Operating Supply

f = fmax = 1/tRC

VCC = VCCmax

15

20

mA

Current

f = 1 MHz

IOUT = 0 mA, CMOS levels

2

2.5

ISB2 [6]

Automatic CE Power

> V

– 0.2V, V

> V

– 0.2V or V

< 0.2V,

1

7

μA

CE

CC

CC

down Current — CMOS

f = 0, V

IN

IN

CC

= VCC(max)

Inputs

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter	Description	Test Conditions	Max	Unit
CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	10	pF
		VCC = VCC(typ)
COUT	Output Capacitance		10	pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter	Description	Test Conditions	TSOP II	Unit
ΘJA	Thermal Resistance	Still Air, soldered on a 3 × 4.5 inch, two layer	77	°C/W
	(Junction to Ambient)	printed circuit board
ΘJC	Thermal Resistance		13	°C/W
	(Junction to Case)

Notes

3.VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.

4.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

5.Full Device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.

6.Only chip enable (CE) and byte enables (BHE and BLE) is tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs are left floating.

Document Number: 001-07970 Rev. *D Page 3 of 11

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