Cypress CY62167E MoBL manual Switching Waveforms

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CY62167E MoBL®

Switching Waveforms

Figure 1 shows address transition controlled read cycle waveforms.[18, 19]

Figure 1. Read Cycle No. 1

tRC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Figure 2 shows OE controlled read cycle waveforms.[19, 20]

Figure 2. Read Cycle No. 2

ADDRESS

 

 

CE1

 

tRC

 

tPD

 

 

CE2

 

tHZCE

 

 

 

tACE

 

BHE/BLE

 

 

 

tDBE

tHZBE

 

tLZBE

 

OE

 

 

 

tDOE

tHZOE

 

tLZOE

HIGH

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

 

DATA VALID

 

 

 

tLZCE

ICC

VCC

tPU

SUPPLY

50%

50%

 

ISB

CURRENT

 

Notes

18.The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

19.WE is HIGH for read cycle.

20.Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

Document #: 001-15607 Rev. *A

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Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor CorporationPin Tsop I Top View Pin Configuration 2Product Portfolio MinOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceData Retention Waveform12 Data Retention CharacteristicsAC Test Loads and Waveforms Parameters Values UnitRead Cycle Switching CharacteristicsParameter Description 45 ns Unit Min Max Write CycleSwitching Waveforms Shows WE controlled write cycle waveforms.17, 21 Data IO Valid DataShows CE1 or CE2 controlled write cycle waveforms.17, 21 Shows BHE/BLE controlled, OE LOW write cycle waveforms.22 Ordering Information Inputs Outputs Mode PowerTruth Table BHE BLEPackage Diagram Pin Tsop I 12 mm x 18.4 mm x 1.0 mmIssue Date Orig. Change Description of Change Document HistoryREV ECN no