Cypress CY62147EV30 manual Switching Characteristics, Min Max Read Cycle, Write Cycle16

CY62147EV30 MoBL®

Switching Characteristics

Over the Operating Range [12, 13]

Parameter			Description	45 ns (Ind’l/Auto-A)		55 ns (Auto-E)		Unit
				Min	Max	Min	Max
Read Cycle
tRC	Read Cycle Time			45		55		ns
tAA	Address to Data Valid				45		55	ns
tOHA	Data Hold from Address Change			10		10		ns
tACE		LOW to Data Valid			45		55	ns
	CE
tDOE		LOW to Data Valid			22		25	ns
	OE
t		LOW to LOW Z[14]		5		5		ns
	OE
LZOE
t		HIGH to High Z[14, 15]			18		20	ns
	OE
HZOE
tLZCE		LOW to Low Z[14]		10		10		ns
	CE
t		HIGH to High Z[14, 15]			18		20	ns
	CE
HZCE
tPU		LOW to Power Up		0		0		ns
	CE
tPD		HIGH to Power Down			45		55	ns
	CE
tDBE					45		55	ns
	BLE/BHE LOW to Data Valid
tLZBE				10		10		ns
	BLE/BHE LOW to Low Z[14]
t					18		20	ns
	BLE/BHE HIGH to HIGH Z[14, 15]
HZBE
Write Cycle[16]
tWC	Write Cycle Time			45		55		ns
tSCE		LOW to Write End		35		40		ns
	CE
tAW	Address Setup to Write End			35		40		ns
tHA	Address Hold from Write End			0		0		ns
tSA	Address Setup to Write Start			0		0		ns
tPWE		Pulse Width		35		40		ns
	WE
tBW				35		40		ns
	BLE/BHE LOW to Write End
tSD	Data Setup to Write End			25		25		ns
tHD	Data Hold from Write End			0		0		ns
t		LOW to High-Z[14, 15]			18		20	ns
	WE
HZWE
tLZWE		HIGH to Low-Z[14]		10		10		ns
	WE

Notes

12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Load and Waveforms on page 4.

13.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

14.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

15.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

16.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 38-05440 Rev. *G Page 5 of 13

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