Cypress CY62146DV30 Thermal Resistance9, AC Test Loads and Waveforms10, Data Retention Waveform

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CY62146DV30

Capacitance (for all packages)[9]

Parameter

 

Description

Test Conditions

 

Max.

 

Unit

 

CIN

 

Input Capacitance

 

TA = 25°C, f = 1 MHz,

 

10

 

pF

 

 

 

 

 

VCC = VCC(typ)

 

 

 

 

 

 

 

COUT

 

Output Capacitance

 

 

10

 

pF

 

Thermal Resistance[9]

 

 

 

 

 

 

 

 

 

 

Parameter

Description

 

Test Conditions

 

BGA

TSOP II

 

Unit

 

 

 

 

 

 

 

 

 

ΘJA

Thermal Resistance

 

Still Air, soldered on a 3 × 4.5 inch, four-layer

 

72

75.13

 

°C/W

 

(Junction to Ambient)

printed circuit board

 

 

 

 

 

 

ΘJC

Thermal Resistance

 

 

 

 

 

8.86

8.95

 

°C/W

 

(Junction to Case)

 

 

 

 

 

 

 

 

 

 

AC Test Loads and Waveforms[10]

R1

VCC

OUTPUT

50 pF

INCLUDING

JIG AND

SCOPE

VCC

 

 

 

 

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

 

90%

 

10%

 

 

 

 

 

 

90%

 

 

 

 

 

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fall Time = 1 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

R2 Rise Time = 1 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Equivalent to:

 

THÉVENIN EQUIVALENT

 

 

 

 

 

 

 

 

 

 

 

 

RTH

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

Parameters

2.50V

3.0V

Unit

R1

16667

1103

 

 

 

 

R2

15385

1554

 

 

 

 

RTH

8000

645

VTH

1.20

1.75

V

Data Retention Characteristics (Over the Operating Range)

Parameter

Description

Conditions

 

Min.

Typ.[5]

Max.

Unit

VDR

VCC for Data Retention

 

 

1.5

 

 

V

ICCDR

Data Retention Current

VCC= 1.5V

L

 

 

 

9

A

 

 

CE > VCC – 0.2V,

 

 

 

 

 

 

 

 

LL

 

 

 

6

 

 

 

VIN > VCC – 0.2V or VIN < 0.2V

 

 

 

 

 

 

tCDR[9]

Chip Deselect to Data Retention Time

 

 

 

0

 

 

ns

t [11]

Operation Recovery Time

 

 

t

RC

 

 

ns

R

 

 

 

 

 

 

 

Data Retention Waveform

 

VCC(min)

DATA RETENTION MODE

VCC(min)

VCC

VDR > 1.5 V

 

tCDR

 

tR

CE

 

 

 

Notes:

9.Tested initially and after any design or process changes that may affect these parameters.

10. Test condition for the 45 ns part is a load capacitance of 30 pF.

11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.

Document #: 38-05339 Rev. *A

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Contents Features Logic Block DiagramFunctional Description1 Cypress Semiconductor CorporationProduct Portfolio Tsop II Top ViewVfbga Top View Typ MaxMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Data Retention Characteristics Over the Operating Range Thermal Resistance9AC Test Loads and Waveforms10 Data Retention WaveformSwitching Characteristics Over the Operating Range Switching Waveforms Read Cycle 1 Address Transition Controlled16Address Data OUT Previous Data ValidWrite Cycle No CE Controlled15, 19 Write Cycle No WE Controlled15, 19Data I/O Write Cycle No BHE/BLE Controlled, OE LOW20 Write Cycle No WE Controlled, OE LOW20DATAI/O Data Inputs/Outputs Mode Power Ordering InformationBHE BLE BV48ALead Vfbga 6 x 8 x 1 mm BV48A Package DiagramPin Tsop II ZS44 Issue Date Orig. Description of Change Document HistoryREV ECN no AJU