Cypress CY14B102N manual AutoStore and Power Up Recall, Software Controlled Store and Recall Cycle

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ADVANCE

CY14E108L, CY14E108N

AutoStore and Power Up RECALL

Parameters

Description

CY14E108L/CY14E108N

Unit

Min

Max

 

 

 

tHRECALL [14]

Power Up RECALL Duration

 

20

ms

tSTORE [15]

STORE Cycle Duration

 

15

ms

VSWITCH

Low Voltage Trigger Level

 

4.4

V

tVCCRISE

VCC Rise Time

150

 

μs

Software Controlled STORE and RECALL Cycle

In the following table, the software controlled STORE/RECALL cycle parameters are listed.[16, 17]

Parameters

Description

20ns

25ns

45ns

Unit

Min

Max

Min

Max

Min

Max

 

 

 

tRC

STORE/RECALL Initiation Cycle Time

20

 

25

 

45

 

ns

tAS

Address Setup Time

0

 

0

 

0

 

ns

tCW

Clock Pulse Width

15

 

20

 

30

 

ns

tGHAX

Address Hold Time

1

 

1

 

1

 

ns

tRECALL

RECALL Duration

 

200

 

200

 

200

μs

tSS [18, 19]

Soft Sequence Processing Time

 

70

 

70

 

70

μs

Hardware STORE Cycle

Parameters

Description

CY14E108L/CY14E108N

Unit

Min

Max

 

 

 

tDELAY [20]

Time allowed to complete SRAM cycle

1

70

μs

tHLHX

Hardware STORE pulse width

15

 

ns

Switching Waveforms

Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 21]

ADDRESS

tRC

tAA

tOHA

DQ (DATA OUT)

DATA VALID

Notes

14.tHRECALL starts from the time VCC rises above VSWITCH.

15.If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.

16.The software sequence is clocked with CE controlled or OE controlled reads.

17.The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.

18.This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.

19.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command

20.On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.

21.HSB must remain HIGH during READ and WRITE cycles.

Document Number: 001-45524 Rev. *A

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtX16 PinoutsTop View Not to scale Pin Definitions Sram Read Hardware Recall Power UpDevice Operation Sram WriteSoftware Store Mode SelectionA15 A0 Mode Power Software RecallData Protection Mode Selection A15 A0 PowerPreventing AutoStore Noise ConsiderationsOperating Range DC Electrical CharacteristicsMaximum Ratings RangeAC Test Conditions CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitSram Read Cycle AC Switching CharacteristicsSram Write Cycle Software Controlled Store and Recall Cycle AutoStore and Power Up RecallHardware Store Cycle Sram Write Cycle #1 WE Controlled 13, 21, 22 Sram Write Cycle #2 CE Controlled13, 21, 22 Α α Hardware Store Cycle20 Ordering Information Part Numbering Nomenclature CY 14 E 108 L ZS P 20 X C TPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Document History Sales, Solutions, and Legal InformationSubmission Orig. Description of Change Date

CY14E108N, CY14B102N specifications

Cypress Semiconductor, a leader in embedded memory solutions, offers a range of non-volatile memory products, among which the CY14B102N and CY14E108N stand out due to their advanced features and robust technology. Both devices are part of Cypress's NVSRAM (Non-Volatile Static Random Access Memory) family, combining the reliability of SRAM with the non-volatility of EEPROM.

The CY14B102N is a 1 Megabit (128 Kilobyte) NVSRAM that utilizes a 2.5V to 3.6V power supply. It features a fast access time of 45 ns, making it suitable for high-speed applications. This device offers a unique advantage by providing data retention for up to 20 years without the need for battery backups, ensuring critical information remains intact even in power-off situations. The CY14B102N also incorporates write cycling endurance rated for over a million cycles, which is ideal for applications requiring frequent data updates.

On the other hand, the CY14E108N features 8 Megabits (1 Megabyte) of NVSRAM, operating at a power supply voltage range of 3.0V to 3.6V. It is designed for higher density applications, while still achieving fast access times of 45 ns. The data retention performance of the CY14E108N similarly allows for up to 20 years of stable data storage under power-off conditions. The device supports a wide range of serial interface protocols, further enhancing its integration capabilities with various microcontrollers and systems.

Both devices implement Cypress's proprietary technology that enables nearly instant data access without requiring a dedicated battery. This makes them suitable for applications in automotive, industrial, consumer, and telecommunications sectors, where maintaining data integrity is critical. The combination of high speed, endurance, and data retention makes the CY14B102N and CY14E108N ideal for systems requiring fast and reliable data storage.

Furthermore, the compatibility of these devices with standard SRAM interfaces ensures seamless integration into existing designs, minimizing design complexity. With their advanced features and reliable performance, Cypress's NVSRAM products provide a compelling solution for high-performance non-volatile memory needs in modern electronic systems.